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IP protection for DSP algorithms' FP...

Dai, Wei.

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IP protection for DSP algorithms' FPGA implementation.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	IP protection for DSP algorithms' FPGA implementation./
作者:	Dai, Wei.
面頁冊數:	78 p.
附註:	Source: Masters Abstracts International, Volume: 43-03, page: 0929.
Contained By:	Masters Abstracts International43-03.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=MQ96386
ISBN:	0612963861

IP protection for DSP algorithms' FPGA implementation.
Dai, Wei.

IP protection for DSP algorithms' FPGA implementation. - 78 p.

Source: Masters Abstracts International, Volume: 43-03, page: 0929.

Thesis (M.A.Sc.)--University of Windsor (Canada), 2004.

With today's system-on-chip (SOC) technology, we are able to design larger and more complicated application-specific integrated circuits (ASICs) and field programmable gate array (FPGA) in shorter time period. The key point of the success of SOC technology is the reuse of intellectual property (IP) cores. Consequently the copyright protection for these IP cores becomes the major concern for the development pace of SOC technology.

ISBN: 0612963861Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

IP protection for DSP algorithms' FPGA implementation.
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500 $a Advisers: H. K. Kwan; H. Wu.
502 $a Thesis (M.A.Sc.)--University of Windsor (Canada), 2004.
520 $a With today's system-on-chip (SOC) technology, we are able to design larger and more complicated application-specific integrated circuits (ASICs) and field programmable gate array (FPGA) in shorter time period. The key point of the success of SOC technology is the reuse of intellectual property (IP) cores. Consequently the copyright protection for these IP cores becomes the major concern for the development pace of SOC technology.
520 $a Watermarking technology has been proved to be an effective way of copyright protection. In this thesis, the author presents two new watermarking algorithms respectively at algorithm level and FPGA layout level. The simulations and implementation results show that the new proposals have much less design and hardware implementation overheads, lower watermark embedding and extraction cost, as well as higher security strength, compared to the previously proposed methods.
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