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Silicon on sapphire CMOS circuits an...

Culurciello, Eugenio.

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Silicon on sapphire CMOS circuits and devices for sensor interfaces.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Silicon on sapphire CMOS circuits and devices for sensor interfaces./
作者:	Culurciello, Eugenio.
面頁冊數:	209 p.
附註:	Source: Dissertation Abstracts International, Volume: 65-11, Section: B, page: 5919.
Contained By:	Dissertation Abstracts International65-11B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3155607
ISBN:	0496163272

Silicon on sapphire CMOS circuits and devices for sensor interfaces.
Culurciello, Eugenio.

Silicon on sapphire CMOS circuits and devices for sensor interfaces. - 209 p.

Source: Dissertation Abstracts International, Volume: 65-11, Section: B, page: 5919.

Thesis (Ph.D.)--The Johns Hopkins University, 2005.

Silicon-On-Insulator (SOI) technologies have recently attracted more and more interest in the development of next-generation high-performance VLSI circuits. The absence of latch-up, the reduced parasitic capacitance, and the isolation and multi-threshold devices are just a few of the advantages of this technology.

ISBN: 0496163272Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Silicon on sapphire CMOS circuits and devices for sensor interfaces.
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245 1 0 $a Silicon on sapphire CMOS circuits and devices for sensor interfaces.
300 $a 209 p.
500 $a Source: Dissertation Abstracts International, Volume: 65-11, Section: B, page: 5919.
500 $a Adviser: Andreas G. Andreou.
502 $a Thesis (Ph.D.)--The Johns Hopkins University, 2005.
520 $a Silicon-On-Insulator (SOI) technologies have recently attracted more and more interest in the development of next-generation high-performance VLSI circuits. The absence of latch-up, the reduced parasitic capacitance, and the isolation and multi-threshold devices are just a few of the advantages of this technology.
520 $a This thesis will introduce a flavor of SOI called Silicon-On-Sapphire (SOS), describing the fabrication process, the advantages and the basic devices available for low-power, low-voltage, high-speed design.
520 $a The objective of this thesis is to accustom the reader to the SOI/SOS fabrication process, starting from the physical constraint of fabrication and moving to device characterization, modeling and ultimately to VLSI systems.
520 $a The physical differences in the fabrication of the SOS devices and the insulating substrate make SOS MOSFETs quite different from a bulk process. While the characteristics of the devices are not significantly different from the devices in a bulk process, the insulating substrate, the floating body and the different thermal properties of the sapphire give rise to characteristics that have to be fully mastered to allow for high-precision design of circuits.
520 $a I will present the design and development of systems in SOS starting with the design of an analog-to-digital converter in SOI/SOS technology. The converter design benefits from the choice of the SOS technology and presents very interesting key design tradeoffs typical of engineering in this technology.
520 $a The insulating substrate of the SOS process allowed me to fabricate the first monolithic digital isolation buffer. I will introduce the design, explain the tradeoffs and report on the performance of this system.
520 $a Subsequently, I will report on a 16 by 16 pixels SOS-CMOS image sensor array fabricated in the SOS process, one of the first standard CMOS image sensor arrays capable of transducing light simultaneously from both sides of the die. This image sensor array was built after a careful analysis of the photosensitive elements in SOS.
590 $a School code: 0098.
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790 1 0 $a Andreou, Andreas G., $e advisor
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791 $a Ph.D.
792 $a 2005
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