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Noise modeling, evaluation and noise...

Ding, Li.

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Noise modeling, evaluation and noise-tolerant design of very deep submicron VLSI circuits.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Noise modeling, evaluation and noise-tolerant design of very deep submicron VLSI circuits./
Author:	Ding, Li.
Description:	156 p.
Notes:	Source: Dissertation Abstracts International, Volume: 65-02, Section: B, page: 0916.
Contained By:	Dissertation Abstracts International65-02B.
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3121921
ISBN:	049669272X

Noise modeling, evaluation and noise-tolerant design of very deep submicron VLSI circuits.
Ding, Li.

Noise modeling, evaluation and noise-tolerant design of very deep submicron VLSI circuits. - 156 p.

Source: Dissertation Abstracts International, Volume: 65-02, Section: B, page: 0916.

Thesis (Ph.D.)--University of Michigan, 2004.

Continuous semiconductor technology scaling has brought the digital circuit noise problem to the forefront. This dissertation investigates the noise problem from three aspects: study the sources of noises and develop fast and accurate noise mode

ISBN: 049669272XSubjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Noise modeling, evaluation and noise-tolerant design of very deep submicron VLSI circuits.
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245 1 0 $a Noise modeling, evaluation and noise-tolerant design of very deep submicron VLSI circuits.
300 $a 156 p.
500 $a Source: Dissertation Abstracts International, Volume: 65-02, Section: B, page: 0916.
500 $a Chair: Pinaki Mazumder.
502 $a Thesis (Ph.D.)--University of Michigan, 2004.
520 $a Continuous semiconductor technology scaling has brought the digital circuit noise problem to the forefront. This dissertation investigates the noise problem from three aspects: study the sources of noises and develop fast and accurate noise mode
520 $a The first part of this dissertation addresses the noise modeling problem for interconnect coupling noises, the dominant source of noises in deep submicron VLSI chips. We have developed a complete framework for crosstalk noise modeling in the pre
520 $a The second part of this dissertation studies the impact of' noises on circuit functionality. We have proposed a maximum square based dynamic noise margin calculation method and developed associated noise margin models to reduce the pessimism of
520 $a The third part of this dissertation describes a novel technique to resolve noise violations by improving the noise tolerant of critical logic gates. We have identified a key property of the keeper network of dynamic logic gates, which opens the
590 $a School code: 0127.
650 4 $a Engineering, Electronics and Electrical. $3 626636
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773 0 $t Dissertation Abstracts International $g 65-02B.
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