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String matching architectures for ne...
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Baker, Zachary.
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String matching architectures for network security on reconfigurable computers.
紀錄類型:
書目-電子資源 : Monograph/item
正題名/作者:
String matching architectures for network security on reconfigurable computers./
作者:
Baker, Zachary.
面頁冊數:
119 p.
附註:
Source: Dissertation Abstracts International, Volume: 67-10, Section: B, page: 5930.
Contained By:
Dissertation Abstracts International67-10B.
標題:
Engineering, Electronics and Electrical. -
電子資源:
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3237155
ISBN:
9780542912085
String matching architectures for network security on reconfigurable computers.
Baker, Zachary.
String matching architectures for network security on reconfigurable computers.
- 119 p.
Source: Dissertation Abstracts International, Volume: 67-10, Section: B, page: 5930.
Thesis (Ph.D.)--University of Southern California, 2006.
Network-connected devices often have vulnerabilities susceptible to exploitation. In order to protect individual systems and the entire network, network operators must ensure that attacks do not traverse their network links. One method for understanding the attacks on a network is an Intrusion Detection System (IDS). Intrusion Detection Systems use sophisticated rules utilizing string matching to detect potential malicious packets. Due to the high string matching rates required, this filtering requires significant computational resources. Fortunately, the computational requirements can be met by Field Programmable Gate Array (FPGA) devices. This thesis describes two efficient hardware string matching architectures developed to provide high levels of time and area performance.
ISBN: 9780542912085Subjects--Topical Terms:
626636
Engineering, Electronics and Electrical.
String matching architectures for network security on reconfigurable computers.
LDR
:03351nmm 2200313 4500
001
1834826
005
20071127121429.5
008
130610s2006 eng d
020
$a
9780542912085
035
$a
(UMI)AAI3237155
035
$a
AAI3237155
040
$a
UMI
$c
UMI
100
1
$a
Baker, Zachary.
$3
1923463
245
1 0
$a
String matching architectures for network security on reconfigurable computers.
300
$a
119 p.
500
$a
Source: Dissertation Abstracts International, Volume: 67-10, Section: B, page: 5930.
500
$a
Adviser: Viktor K. Prasanna.
502
$a
Thesis (Ph.D.)--University of Southern California, 2006.
520
$a
Network-connected devices often have vulnerabilities susceptible to exploitation. In order to protect individual systems and the entire network, network operators must ensure that attacks do not traverse their network links. One method for understanding the attacks on a network is an Intrusion Detection System (IDS). Intrusion Detection Systems use sophisticated rules utilizing string matching to detect potential malicious packets. Due to the high string matching rates required, this filtering requires significant computational resources. Fortunately, the computational requirements can be met by Field Programmable Gate Array (FPGA) devices. This thesis describes two efficient hardware string matching architectures developed to provide high levels of time and area performance.
520
$a
The Knuth-Morris-Pratt (KMP) algorithm is an efficient string matching technique that requires a minimum of comparisons through the use of a pre-computed transition table. This thesis presents a modification of the basic algorithm that allows its use in an efficient hardware architecture, allowing the system to accept at least one character in each cycle. The memory-based units allow runtime pattern reconfiguration. A major contribution is a proof of the worst-case buffer size requirement such that throughput is maintained with no chance of a false negative. The buffered KMP algorithm reduces the overall work done, and thereby the area required is lower as well.
520
$a
In another approach, a set of tools was developed for automatic synthesis of highly efficient intrusion detection systems. This approach uses a high-level, graph-based partitioning methodology to produce "hardwired" architectures compiled to the FPGA device. The automated design techniques and architecture allows faster clock rates and extensive reuse of hardware components for dramatic increases in area-time performance. Through design-time compilation, the methodology yields designs that take advantage of pattern redundancy. To extend the capabilities of the hardwired architectures, extensions were developed that provide support for rules requiring string literal extensions including wild-card separated patterns with bounding restrictions.
520
$a
By combining the two techniques into a hybrid system, improvements in terms of area, memory efficiency, and frequency performance are achieved, while providing on-the-fly reprogramming.
590
$a
School code: 0208.
650
4
$a
Engineering, Electronics and Electrical.
$3
626636
650
4
$a
Computer Science.
$3
626642
690
$a
0544
690
$a
0984
710
2 0
$a
University of Southern California.
$3
700129
773
0
$t
Dissertation Abstracts International
$g
67-10B.
790
1 0
$a
Prasanna, Viktor K.,
$e
advisor
790
$a
0208
791
$a
Ph.D.
792
$a
2006
856
4 0
$u
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3237155
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