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The design and synthesis of concurre...
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Tugsinavisut, Sunan.
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The design and synthesis of concurrent asynchronous systems .
紀錄類型:
書目-電子資源 : Monograph/item
正題名/作者:
The design and synthesis of concurrent asynchronous systems ./
作者:
Tugsinavisut, Sunan.
面頁冊數:
162 p.
附註:
Source: Dissertation Abstracts International, Volume: 67-10, Section: B, page: 5969.
Contained By:
Dissertation Abstracts International67-10B.
標題:
Engineering, Electronics and Electrical. -
電子資源:
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3237182
ISBN:
9780542912887
The design and synthesis of concurrent asynchronous systems .
Tugsinavisut, Sunan.
The design and synthesis of concurrent asynchronous systems .
- 162 p.
Source: Dissertation Abstracts International, Volume: 67-10, Section: B, page: 5969.
Thesis (Ph.D.)--University of Southern California, 2006.
This dissertation explores the design and synthesis of concurrent asynchronous systems. In the first part, we perform an extensive case study of a DCT matrix-vector multiplier using several different micro-architectural designs and circuit styles. This includes a bundled-data implementation that motivates the development of efficient control circuit templates. By adopting templates that can easily handle complex control, the designer can save significant design time. In addition, a quasi-delay-insensitive (QDI) implementation motivates design exploration of several different micro-architectural tradeoffs and optimizations. Experimental results comparing these designs to a full-custom synchronous counterpart show that various implementations yield different advantages. The bundled-data designs achieve higher average performance with negligible power and area increases, while the QDI designs provide much higher throughput, more robust to process variations, and reduced design time at the expense of higher power and larger area.
ISBN: 9780542912887Subjects--Topical Terms:
626636
Engineering, Electronics and Electrical.
The design and synthesis of concurrent asynchronous systems .
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In the second part, we present a high-level synthesis framework for highly concurrent systems that can handle multi-threading and pipelined behaviors, which are typical in asynchronous systems. We propose the use of marked graphs because they can naturally express highly concurrent systems. We address several issues relating to the cyclic nature of marked graphs and propose both exact and heuristic performance-driven scheduling and allocation algorithms. The scheduling and allocation algorithms, however, do not address the binding problem. Hence, we propose performance-driven concurrent scheduling and binding algorithms: one exact algorithm and one heuristic algorithm. A coloring approach is used to formulate and solve the binding problem. Experimental results show the performance and area tradeoffs of various designs by controlling concurrency in the design and also highlight the tradeoffs of the proposed exact and heuristic algorithms.
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