語系:
繁體中文
English
說明(常見問題)
回圖書館首頁
手機版館藏查詢
登入
回首頁
切換:
標籤
|
MARC模式
|
ISBD
Contemporary data path design optimi...
~
Liu, Jianhua.
FindBook
Google Book
Amazon
博客來
Contemporary data path design optimization.
紀錄類型:
書目-電子資源 : Monograph/item
正題名/作者:
Contemporary data path design optimization./
作者:
Liu, Jianhua.
面頁冊數:
94 p.
附註:
Source: Dissertation Abstracts International, Volume: 67-04, Section: B, page: 2084.
Contained By:
Dissertation Abstracts International67-04B.
標題:
Computer Science. -
電子資源:
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3214712
ISBN:
9780542639784
Contemporary data path design optimization.
Liu, Jianhua.
Contemporary data path design optimization.
- 94 p.
Source: Dissertation Abstracts International, Volume: 67-04, Section: B, page: 2084.
Thesis (Ph.D.)--University of California, San Diego, 2006.
As the core of most digital computing systems, data-path design is essential to determine the whole system performance. In the past decades many advanced methodologies and technologies have been proposed to optimize data-path designs. Nowadays new design requirements are emerging with the technology development: (1) Low power design. Power consumption becomes more critical issue than performance in modern data-path designs, especially for mobile device applications. (2) Extremely high performance design for micro processors. With the shrink of feature size and the increase of clock frequency, extremely high performance data-path components operated on multiple giga-hertz clock are required in micro processor designs. (3) High performance low cost design for ASIC. Application-specific design constraints, such as area/power budget and non-uniform signal required times, must be satisfied.
ISBN: 9780542639784Subjects--Topical Terms:
626642
Computer Science.
Contemporary data path design optimization.
LDR
:03535nmm 2200313 4500
001
1832042
005
20070628102642.5
008
130610s2006 eng d
020
$a
9780542639784
035
$a
(UnM)AAI3214712
035
$a
AAI3214712
040
$a
UnM
$c
UnM
100
1
$a
Liu, Jianhua.
$3
1920795
245
1 0
$a
Contemporary data path design optimization.
300
$a
94 p.
500
$a
Source: Dissertation Abstracts International, Volume: 67-04, Section: B, page: 2084.
500
$a
Adviser: Chung-Kuan Cheng.
502
$a
Thesis (Ph.D.)--University of California, San Diego, 2006.
520
$a
As the core of most digital computing systems, data-path design is essential to determine the whole system performance. In the past decades many advanced methodologies and technologies have been proposed to optimize data-path designs. Nowadays new design requirements are emerging with the technology development: (1) Low power design. Power consumption becomes more critical issue than performance in modern data-path designs, especially for mobile device applications. (2) Extremely high performance design for micro processors. With the shrink of feature size and the increase of clock frequency, extremely high performance data-path components operated on multiple giga-hertz clock are required in micro processor designs. (3) High performance low cost design for ASIC. Application-specific design constraints, such as area/power budget and non-uniform signal required times, must be satisfied.
520
$a
Inspired by these requirements, we propose two optimization techniques to efficiently minimize power consumption and achieve timing/area/power tradeoff for specific applications.
520
$a
1. Binary addition is the most widely used fundamental operations. Various applications require different adder designs for high speed, small area or low power consumption. Since parallel prefix adders provide great flexibility to satisfy a specific application, we propose an integer linear programming method to build optimal prefix adders, which counts gate and wire capacitances in the timing and power models. Furthermore the proposed method can handle nonuniform arrival time and required time on each bit position. Therefore, a realistic minimal-power prefix adder can be found with arbitrary timing and area constraints.
520
$a
2. Division is a fundamental but expensive arithmetic operation. We analyze the computation efforts from memory, arithmetic functions and iterations in division operation and propose a hybrid algorithm which employs Prescaling, Series expansion and Taylor expansion (PST) algorithms together. The proposed algorithm boosts very-high radix division by efficiently estimating the reciprocal of divisor, and achieves outstanding performance-cost tradeoff. Optimizations of the basic PST algorithm are also developed to improve the performance further. The proposed algorithm is suitable for both ASIC and FPGA applications with high-performance division units.
520
$a
These research works optimize data-path designs in different levels from algorithm to logical/physical synthesis. Unlike the previous works, both approaches proposed in the dissertation explore the design space in terms of timing, area and power consumption.
590
$a
School code: 0033.
650
4
$a
Computer Science.
$3
626642
690
$a
0984
710
2 0
$a
University of California, San Diego.
$3
1018093
773
0
$t
Dissertation Abstracts International
$g
67-04B.
790
1 0
$a
Cheng, Chung-Kuan,
$e
advisor
790
$a
0033
791
$a
Ph.D.
792
$a
2006
856
4 0
$u
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3214712
筆 0 讀者評論
館藏地:
全部
電子資源
出版年:
卷號:
館藏
1 筆 • 頁數 1 •
1
條碼號
典藏地名稱
館藏流通類別
資料類型
索書號
使用類型
借閱狀態
預約狀態
備註欄
附件
W9222905
電子資源
11.線上閱覽_V
電子書
EB
一般使用(Normal)
在架
0
1 筆 • 頁數 1 •
1
多媒體
評論
新增評論
分享你的心得
Export
取書館
處理中
...
變更密碼
登入