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Design of a 14-bit continuous-time d...
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Li, Zhimin.
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Design of a 14-bit continuous-time delta-sigma A/D modulator with 2.5MHz signal bandwidth.
紀錄類型:
書目-電子資源 : Monograph/item
正題名/作者:
Design of a 14-bit continuous-time delta-sigma A/D modulator with 2.5MHz signal bandwidth./
作者:
Li, Zhimin.
面頁冊數:
139 p.
附註:
Source: Dissertation Abstracts International, Volume: 67-02, Section: B, page: 1059.
Contained By:
Dissertation Abstracts International67-02B.
標題:
Engineering, Electronics and Electrical. -
電子資源:
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3207151
ISBN:
9780542541612
Design of a 14-bit continuous-time delta-sigma A/D modulator with 2.5MHz signal bandwidth.
Li, Zhimin.
Design of a 14-bit continuous-time delta-sigma A/D modulator with 2.5MHz signal bandwidth.
- 139 p.
Source: Dissertation Abstracts International, Volume: 67-02, Section: B, page: 1059.
Thesis (Ph.D.)--Oregon State University, 2006.
In recent years, there has been growing interest in both industry and academia to use continuous-time (CT) Delta-Sigma A/D converters for wideband wireless and wireline communication applications.
ISBN: 9780542541612Subjects--Topical Terms:
626636
Engineering, Electronics and Electrical.
Design of a 14-bit continuous-time delta-sigma A/D modulator with 2.5MHz signal bandwidth.
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Source: Dissertation Abstracts International, Volume: 67-02, Section: B, page: 1059.
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Adviser: Terri S. Fiez.
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Thesis (Ph.D.)--Oregon State University, 2006.
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In recent years, there has been growing interest in both industry and academia to use continuous-time (CT) Delta-Sigma A/D converters for wideband wireless and wireline communication applications.
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So far no reported CT Delta-Sigma A/D modulator achieves 14-bit or higher dynamic range (DR) with more than 2MHz signal bandwidth (equivalently 4MS/s). This dissertation presents the realization of a continuous-time (CT) Delta-Sigma A/D modulator providing 80.5dB DR and 85dB DR with 5MS/s output data rate in a 2.5V 0.25mum CMOS process. The modulator has a single-stage dual-loop architecture allowing large quantizer delay. A 17-level quantizer is used to increase resolution and non-return-to-zero DACs are adopted to reduce clock jitter sensitivity. Capacitor tuning is utilized to overcome time-constant variation. On-chip self-calibration is implemented to suppress DAC nonlinearity. Combining techniques to address various design challenges, the modulator consumes 50mW with 60MHz sampling rate.
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