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Adaptive blocker rejection continuou...

Kim, Hyung Seok.

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Adaptive blocker rejection continuous-time sigma-delta ADC.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Adaptive blocker rejection continuous-time sigma-delta ADC./
作者:	Kim, Hyung Seok.
面頁冊數:	113 p.
附註:	Source: Dissertation Abstracts International, Volume: 71-05, Section: B, page: 3248.
Contained By:	Dissertation Abstracts International71-05B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3407142
ISBN:	9781109747287

Adaptive blocker rejection continuous-time sigma-delta ADC.
Kim, Hyung Seok.

Adaptive blocker rejection continuous-time sigma-delta ADC. - 113 p.

Source: Dissertation Abstracts International, Volume: 71-05, Section: B, page: 3248.

Thesis (Ph.D.)--Arizona State University, 2010.

The current trend in radio frequency receiver design is to move digital signals as close as possible to an antenna and then perform most of the signal processing in the digital domain. This enables receiver complexity to be reduced and allows higher integration of the circuits in complementary metal-oxide-semiconductor (CMOS) processes. However, this approach also requires development of a high performance, low power, low complexity analog-to-digital convert (ADC), which is a challenging task in deep submicron CMOS processes.

ISBN: 9781109747287Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Adaptive blocker rejection continuous-time sigma-delta ADC.
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500 $a Source: Dissertation Abstracts International, Volume: 71-05, Section: B, page: 3248.
502 $a Thesis (Ph.D.)--Arizona State University, 2010.
520 $a The current trend in radio frequency receiver design is to move digital signals as close as possible to an antenna and then perform most of the signal processing in the digital domain. This enables receiver complexity to be reduced and allows higher integration of the circuits in complementary metal-oxide-semiconductor (CMOS) processes. However, this approach also requires development of a high performance, low power, low complexity analog-to-digital convert (ADC), which is a challenging task in deep submicron CMOS processes.
520 $a This thesis focuses on the development of an adaptive blocker-rejection wideband continuous-time sigma-delta ADC (CT SigmaDelta ADC). An integrated blocker detector reconfigures the ADC architecture in real time to reject interference, which improves the selectivity and sensitivity of the receiver without increasing its dynamic-range requirements. To minimize power consumption, the ADC uses a built-in high-pass filter that performs blocker-level detection without utilizing any additional circuitry. The adaptive operation relaxes baseband channel-filtering requirements for a WiMAX receiver.
520 $a The proposed ADC has been integrated in a 130nm CMOS process occupying a silicon area of 1.5x0.9mm2 The CT SigmaDelta ADC achieves 70dB of DR, 65dB of peak signal to noise-plus-distortion ratio (SNDR), and 68dB of peak signal to noise ratio (SNR) over a 10MHz signal bandwidth, consuming 18mW from a 1.2V supply. The ADC reconfigures the loop-filter topology within 50micros without any transient impact on bit-error rate. In the blocker-suppression mode, the ADC can withstand 30dBc blocker at the adjacent channel, achieving -22dB error-vector magnitude with a 24Mbps 16-QAM signal.
590 $a School code: 0010.
650 4 $a Engineering, Electronics and Electrical. $3 626636
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710 2 $a Arizona State University. $3 1017445
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