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Multi-threshold CMOS circuit design ...

Thian, Ross.

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Multi-threshold CMOS circuit design methodology from 2D to 3D.

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Multi-threshold CMOS circuit design methodology from 2D to 3D./
Author:	Thian, Ross.
Description:	97 p.
Notes:	Source: Masters Abstracts International, Volume: 49-02, page: .
Contained By:	Masters Abstracts International49-02.
Subject:	Engineering, Computer. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=1482775
ISBN:	9781124309323

Multi-threshold CMOS circuit design methodology from 2D to 3D.
Thian, Ross.

Multi-threshold CMOS circuit design methodology from 2D to 3D. - 97 p.

Source: Masters Abstracts International, Volume: 49-02, page: .

Thesis (M.S.Cmp.E.)--University of Arkansas, 2010.

A new and exciting approach in digital IC design in order to accommodate the Moore's law is 3D chip stacking. Chip stacking offers more transistors per chip, reduced wire lengths, and increased memory access bandwidths. This thesis demonstrates that traditional 2D design flow can be adapted for 3D chip stacking. 3D chip stacking has a serious drawback: heat generation. Die-on-die architecture reduces exposed surface area for heat dissipation. In order to reduce heat generation, a low power technique named Multi-Threshold CMOS (MTCMOS) was incorporated in this work. MTCMOS required designing a power management unit (to control when and which gates are powered), a MTCMOS gate library, and a state saving D-Flip-Flop. This thesis demonstrates converting a traditional 2D chip to a low heat 3D chip design with the use of MTCMOS technology using industry-standard CAD tools.

ISBN: 9781124309323Subjects--Topical Terms:

1669061
Engineering, Computer.

Multi-threshold CMOS circuit design methodology from 2D to 3D.
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245 1 0 $a Multi-threshold CMOS circuit design methodology from 2D to 3D.
300 $a 97 p.
500 $a Source: Masters Abstracts International, Volume: 49-02, page: .
500 $a Adviser: Jia Di.
502 $a Thesis (M.S.Cmp.E.)--University of Arkansas, 2010.
520 $a A new and exciting approach in digital IC design in order to accommodate the Moore's law is 3D chip stacking. Chip stacking offers more transistors per chip, reduced wire lengths, and increased memory access bandwidths. This thesis demonstrates that traditional 2D design flow can be adapted for 3D chip stacking. 3D chip stacking has a serious drawback: heat generation. Die-on-die architecture reduces exposed surface area for heat dissipation. In order to reduce heat generation, a low power technique named Multi-Threshold CMOS (MTCMOS) was incorporated in this work. MTCMOS required designing a power management unit (to control when and which gates are powered), a MTCMOS gate library, and a state saving D-Flip-Flop. This thesis demonstrates converting a traditional 2D chip to a low heat 3D chip design with the use of MTCMOS technology using industry-standard CAD tools.
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