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具容忍時序錯誤之心脈陣列的設計架構 = = A Design Fram...

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具容忍時序錯誤之心脈陣列的設計架構 = = A Design Framework of Systolic Arrays for Tolerating Timing Errors /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	具容忍時序錯誤之心脈陣列的設計架構 = / 賴俊年撰
Reminder of title:	A Design Framework of Systolic Arrays for Tolerating Timing Errors /
remainder title:	A Design Framework of Systolic Arrays for Tolerating Timing Errors
Author:	賴俊年
other author:	紀新洲
Published:	[花蓮縣壽豐鄉] : [國立東華大學電機工程學系], : 2012[民101],
Description:	11,82面 : 圖,表 ; 30公分
Notes:	指導教授:紀新洲
Online resource:	http://134.208.29.93/cgi-bin/cdrfb3/gsweb.cgi?ccd=xZ3ZHR&o=e2&dbid=I%2B3%3D%3C19%2A%3B%25%2B&dbpathf=/opt/cdrfb3/db/stdcdrf/&fuid=01&dbna=

具容忍時序錯誤之心脈陣列的設計架構 = = A Design Framework of Systolic Arrays for Tolerating Timing Errors /
賴俊年

具容忍時序錯誤之心脈陣列的設計架構 = A Design Framework of Systolic Arrays for Tolerating Timing Errors / A Design Framework of Systolic Arrays for Tolerating Timing Errors賴俊年撰 - 初版 - [花蓮縣壽豐鄉] : [國立東華大學電機工程學系], 2012[民101] - 11,82面 : 圖,表 ; 30公分

指導教授:紀新洲

碩士論文-- 國立東華大學電機工程學系

參考書目:面80-82

贈閱Subjects--Index Terms:

系統晶片

具容忍時序錯誤之心脈陣列的設計架構 = = A Design Framework of Systolic Arrays for Tolerating Timing Errors /
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653 0 $a 錯誤復原
653 0 $a 積體電路
653 0 $a system of chip
653 0 $a systolic arrays
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653 0 $a error resilient
653 0 $a integrated circuit design
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700 1 $a Chi, Hsin-Chou $3 3032907
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