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HotSpot: A chip and package compact ...

Huang, Wei.

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HotSpot: A chip and package compact thermal modeling methodology for VLSI design.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	HotSpot: A chip and package compact thermal modeling methodology for VLSI design./
作者:	Huang, Wei.
面頁冊數:	139 p.
附註:	Adviser: Mircea R. Stan.
Contained By:	Dissertation Abstracts International67-11B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3239977
ISBN:	9780542948039

HotSpot: A chip and package compact thermal modeling methodology for VLSI design.
Huang, Wei.

HotSpot: A chip and package compact thermal modeling methodology for VLSI design. - 139 p.

Adviser: Mircea R. Stan.

Thesis (Ph.D.)--University of Virginia, 2007.

To deal with the challenges of managing the ever-increasing power densities and temperatures of VLSI systems, thermal models have become more and more important for performing thermal analysis during design time. Due to their lumped thermal R-C network nature, compact thermal models are simple and efficient for thermal analysis in VLSI design, especially during early design stages, where detailed layout information is not available. Additionally, temperature predictions from compact thermal models can also be utilized to develop architecture-level run-time thermal management techniques. However, existing compact thermal modeling approaches have a number of limitations, such as not providing detailed temperature distributions, or using unrealistic assumptions for package modeling, or being restricted to particular packages, or being not parameterizable.

ISBN: 9780542948039Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

HotSpot: A chip and package compact thermal modeling methodology for VLSI design.
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245 1 0 $a HotSpot: A chip and package compact thermal modeling methodology for VLSI design.
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502 $a Thesis (Ph.D.)--University of Virginia, 2007.
520 $a To deal with the challenges of managing the ever-increasing power densities and temperatures of VLSI systems, thermal models have become more and more important for performing thermal analysis during design time. Due to their lumped thermal R-C network nature, compact thermal models are simple and efficient for thermal analysis in VLSI design, especially during early design stages, where detailed layout information is not available. Additionally, temperature predictions from compact thermal models can also be utilized to develop architecture-level run-time thermal management techniques. However, existing compact thermal modeling approaches have a number of limitations, such as not providing detailed temperature distributions, or using unrealistic assumptions for package modeling, or being restricted to particular packages, or being not parameterizable.
520 $a This dissertation presents HotSpot---a novel modeling methodology for developing compact thermal models based on the popular stacked-layer packaging scheme in modern VLSI systems. In addition to modeling silicon and packaging layers, HotSpot also includes a high-level on-chip interconnects self-heating power and thermal model such that the thermal impact of interconnects can also be considered during early design stages. The HotSpot compact thermal modeling approach is especially well suited for pre-RTL and pre-synthesis thermal analysis and is able to provide detailed static and transient temperature information across the die and the package, it is also computationally efficient and fully parameterizable. HotSpot compact thermal models have been validated with detailed numerical simulations, thermal test chip and temperature measurements of an FPGA-based SoC design. It is also shown to be boundary condition independent. Example applications demonstrate how our modeling approach helps in developing dynamic thermal management techniques and provides more accurate design estimations for temperature, leakage power, delay and reliability in a temperature-aware design flow. The presented HotSpot modeling method can also be easily extended to model emerging packaging schemes such as stacked chip-scale packaging (SCP) and 3-D integration.
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