東華大學圖書館 |

Language: English

Help

回圖書館首頁

手機版館藏查詢

Back

Switch To: Labeled | MARC Mode | ISBD

Layout-level circuit sizing and desi...

Mukherjee, Souvik.

Linked to FindBook

Google Book

Amazon

博客來

Layout-level circuit sizing and design-for-manufacturability methods for embedded passive RF circuits.

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Layout-level circuit sizing and design-for-manufacturability methods for embedded passive RF circuits./
Author:	Mukherjee, Souvik.
Description:	215 p.
Notes:	Adviser: Madhavan Swaminathan.
Contained By:	Dissertation Abstracts International68-07B.
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3271567
ISBN:	9780549108016

Layout-level circuit sizing and design-for-manufacturability methods for embedded passive RF circuits.
Mukherjee, Souvik.

Layout-level circuit sizing and design-for-manufacturability methods for embedded passive RF circuits. - 215 p.

Adviser: Madhavan Swaminathan.

Thesis (Ph.D.)--Georgia Institute of Technology, 2007.

The emergence of multi-band communications standards, and the fast pace of the consumer electronics market for wireless/cellular applications emphasize the needs for fast design closure. In addition, there is a need for electronic product designers to collaborate with manufacturers, gain essential knowledge regarding the manufacturing facilities and the processes, and apply this knowledge during the design process. In this dissertation, efficient layout-level circuit sizing techniques, and methodologies for design-for-manufacturability have been investigated.

ISBN: 9780549108016Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Layout-level circuit sizing and design-for-manufacturability methods for embedded passive RF circuits.
LDR:03317nam 2200289 a 45 001 947384
005 20110524
008 110524s2007 eng d
020 $a 9780549108016
035 $a (UMI)AAI3271567
035 $a AAI3271567
040 $a UMI $c UMI
100 1 $a Mukherjee, Souvik. $3 1270855
245 1 0 $a Layout-level circuit sizing and design-for-manufacturability methods for embedded passive RF circuits.
300 $a 215 p.
500 $a Adviser: Madhavan Swaminathan.
500 $a Source: Dissertation Abstracts International, Volume: 68-07, Section: B, page: 4715.
502 $a Thesis (Ph.D.)--Georgia Institute of Technology, 2007.
520 $a The emergence of multi-band communications standards, and the fast pace of the consumer electronics market for wireless/cellular applications emphasize the needs for fast design closure. In addition, there is a need for electronic product designers to collaborate with manufacturers, gain essential knowledge regarding the manufacturing facilities and the processes, and apply this knowledge during the design process. In this dissertation, efficient layout-level circuit sizing techniques, and methodologies for design-for-manufacturability have been investigated.
520 $a For cost-effective fabrication of RF modules on emerging technologies, there is a clear need for design cycle time reduction of passive and active RF modules. This is important since new technologies lack extensive design libraries and layout-level electromagnetic (EM) optimization of RF circuits becomes the major bottleneck for reduced design time. In addition, the design of multi-band RF circuits requires precise control of design specifications that are partially satisfied due to manufacturing variations, resulting in yield loss. In this work, a broadband modeling and a layout-level synthesis technique for embedded inductors/capacitors in multilayer substrate has been presented. The methodology employs artificial neural networks to develop a neuro-model for the embedded passives. Secondly, a layout-level sizing technique for RF passive circuits with quasi-lumped embedded inductors and capacitors has been demonstrated. The sizing technique is based on the circuit augmentation technique and a linear optimization framework.
520 $a In addition, this dissertation presents a layout-level, multi-domain DFM methodology and yield optimization technique for embedded RF circuits for SOP-based wireless applications. The proposed statistical diagnosis technique is based on layout segmentation, lumped element modeling, sensitivity analysis and extraction of probability density function using convolution methods. The statistical analysis takes into account the effect of the thermo-mechanical stress and the process variations that are incurred in batch fabrication. Yield enhancement and optimization methods based on joint probability distribution and constraint-based convex programming has also been presented. The results in this work have been demonstrated to show good correlation with measurement data.
590 $a School code: 0078.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 0 $a Georgia Institute of Technology. $3 696730
773 0 $t Dissertation Abstracts International $g 68-07B.
790 $a 0078
790 1 0 $a Swaminathan, Madhavan, $e advisor
791 $a Ph.D.
792 $a 2007
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3271567