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Minimizing and exploiting leakage in...

Jayakumar, Nikhil.

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Minimizing and exploiting leakage in VLSI.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Minimizing and exploiting leakage in VLSI./
作者:	Jayakumar, Nikhil.
面頁冊數:	166 p.
附註:	Adviser: Sunil P. Khatri.
Contained By:	Dissertation Abstracts International68-06B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3270350
ISBN:	9780549093299

Minimizing and exploiting leakage in VLSI.
Jayakumar, Nikhil.

Minimizing and exploiting leakage in VLSI. - 166 p.

Adviser: Sunil P. Khatri.

Thesis (Ph.D.)--Texas A&M University, 2007.

Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally dynamic (switching) power has dominated the total power consumption of VLSI circuits. However, due to process scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. This dissertation explores techniques to reduce leakage, as well as techniques to exploit leakage currents through the use of sub-threshold circuits.

ISBN: 9780549093299Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Minimizing and exploiting leakage in VLSI.
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245 1 0 $a Minimizing and exploiting leakage in VLSI.
300 $a 166 p.
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502 $a Thesis (Ph.D.)--Texas A&M University, 2007.
520 $a Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally dynamic (switching) power has dominated the total power consumption of VLSI circuits. However, due to process scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. This dissertation explores techniques to reduce leakage, as well as techniques to exploit leakage currents through the use of sub-threshold circuits.
520 $a This dissertation consists of two studies. In the first study, techniques to reduce leakage are presented. These include a low leakage ASIC design methodology that uses high VT sleep transistors selectively, a methodology that combines input vector control and circuit modification, and a scheme to find the optimum reverse body bias voltage to minimize leakage.
520 $a As the minimum feature size of VLSI fabrication processes continues to shrink with each successive process generation (along with the value of supply voltage and therefore the threshold voltage of the devices), leakage currents increase exponentially. Leakage currents are hence seen as a necessary evil in traditional VLSI design methodologies. We present an approach to turn this problem into an opportunity. In the second study in this dissertation, we attempt to exploit leakage currents to perform computation. We use sub-threshold digital circuits and come up with ways to get around some of the pitfalls associated with sub-threshold circuit design. These include a technique that uses body biasing adaptively to compensate for Process, Voltage and Temperature (PVT) variations, a design approach that uses asynchronous micro-pipelined Network of Programmable Logic Arrays (NPLAs) to help improve the throughput of sub-threshold designs, and a method to find the optimum supply voltage that minimizes energy consumption in a circuit.
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