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Security designs for uni- and multi-...

Gao, Lan.

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Security designs for uni- and multi-processors.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Security designs for uni- and multi-processors./
作者:	Gao, Lan.
面頁冊數:	152 p.
附註:	Adviser: Jun Yang.
Contained By:	Dissertation Abstracts International68-09B.
標題:	Computer Science. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3281660
ISBN:	9780549226017

Security designs for uni- and multi-processors.
Gao, Lan.

Security designs for uni- and multi-processors. - 152 p.

Adviser: Jun Yang.

Thesis (Ph.D.)--University of California, Riverside, 2007.

With the prevalence of Internet, software executing on a broad range of systems are constantly subject to malicious attacks in various forms. As a result, program execution may be tampered with, and data confidentiality may be compromised, both causing substantial damages. Most efforts in enhancing computer security have focused on hardening software applications and operating systems. Unfortunately, as more sophisticated and harmful attacks are being developed, there is no one-size-fits-all security solution based purely on software clue to the large code size and complex functionalities.

ISBN: 9780549226017Subjects--Topical Terms:

626642
Computer Science.

Security designs for uni- and multi-processors.
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502 $a Thesis (Ph.D.)--University of California, Riverside, 2007.
520 $a With the prevalence of Internet, software executing on a broad range of systems are constantly subject to malicious attacks in various forms. As a result, program execution may be tampered with, and data confidentiality may be compromised, both causing substantial damages. Most efforts in enhancing computer security have focused on hardening software applications and operating systems. Unfortunately, as more sophisticated and harmful attacks are being developed, there is no one-size-fits-all security solution based purely on software clue to the large code size and complex functionalities.
520 $a This dissertation proposes to provide security protection at the microarchitecture level. The objective is to develop a secure processor model as the foundation of secure program execution, so that user applications are protected from being attacked through the OS, the external memory and the system bus. The existing microprocessor architecture is augmented to incorporate new features. The proposed secure processor design keeps the program code and data in strict confidentiality and maintains their integrity during execution. Moreover, it hides the program control flow and prevents critical information leakage on the address bus.
520 $a In particular, this dissertation presents the following security designs. On uniprocessors, a, pseudo One-Time Pad (OTP) scheme and an on-chip Sequence Number Cache (SNC) are designed to overlap the cryptography computation with the memory accesses, thus minimizing performance penalty. On symmetric shared memory multiprocessors, a CBC-AES-based scheme and an on-chip Secure Hardware Unit (SHU) are developed to encrypt and authenticate cache-to-cache transactions, thus protecting shared bus communication. On the address bus, a low-cost memory remapping scheme is proposed to permute a, dynamic set of on-chip blocks, thus randomizing address patterns on the bus.
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