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The design of high-throughput asynch...

Singh, Montek.

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The design of high-throughput asynchronous pipelines.

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	The design of high-throughput asynchronous pipelines./
作者:	Singh, Montek.
面頁冊數:	242 p.
附註:	Adviser: Steven M. Nowick.
Contained By:	Dissertation Abstracts International62-12B
標題:	Computer Science -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3037758
ISBN:	0493509682

The design of high-throughput asynchronous pipelines.
Singh, Montek.

The design of high-throughput asynchronous pipelines. - 242 p.

Adviser: Steven M. Nowick.

Thesis (Ph.D.)--Columbia University, 2002.

This thesis focuses on the design of very high-speed asynchronous systems. A more specific focus of this thesis is on high-throughput asynchronous pipelines, since pipelining is at the heart of most high-performance systems.

ISBN: 0493509682Subjects--Topical Terms:

890869
Computer Science

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500 $a Source: Dissertation Abstracts International, Volume: 62-12, Section: B, page: 5814.
502 $a Thesis (Ph.D.)--Columbia University, 2002.
520 $a This thesis focuses on the design of very high-speed asynchronous systems. A more specific focus of this thesis is on high-throughput asynchronous pipelines, since pipelining is at the heart of most high-performance systems.
520 $a This thesis makes three contributions.
520 $a Clocked or <italic>synchronous</italic> design has traditionally been used for nearly all digital systems. However, it is now facing significant challenges as clock rates reach several GigaHertz, chip sizes increase, and the demands for low power and modular design become paramount. An alternative paradigm is clockless or <italic>asynchronous</italic> design, which has several potential advantages towards meeting these challenges.
520 $a First, four new asynchronous pipeline styles are introduced: “lookahead,” “high-capacity,” “MOUSETRAP” and “dynamic GasP” pipelines. The styles differ from each other in many aspects, such as handshaking protocols, storage capacity, implementation styles, and timing assumptions. The new styles are capable of multi-GigaHertz throughputs in today's silicon technology (<italic>e.g.</italic>, 0.13–0.18 micron), yet each style has a simple implementation. High throughputs are obtained through efficient pipelining of systems at a fine granularity, though the pipeline styles are also useful for coarser-grain applications
520 $a Next, the basic pipeline styles are extended to address several issues that arise in practice while designing real-world systems. In particular, the styles are generalized to handle a greater variety of architectures (<italic> e.g.</italic>, datapaths with forks and joins), and to robustly interface with arbitrary-speed environments
520 $a Finally, the pipeline styles of this thesis are validated by designing and fabricating real VLSI subsystems, including: simple FIFO's, pipelined adders, and an experimental digital FIR filter chip. All chips were tested to be fully functional; throughputs of over 2.4 GHz for the FIFO's, and up to 1.3 GHz for the FIR filter, were obtained in an IBM 0.18 micron technology
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