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Low-voltage high-speed switched capa...
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Wang, Lei.
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Low-voltage high-speed switched capacitor circuit design.
紀錄類型:
書目-語言資料,印刷品 : Monograph/item
正題名/作者:
Low-voltage high-speed switched capacitor circuit design./
作者:
Wang, Lei.
面頁冊數:
81 p.
附註:
Chair: S. H. K. Embabi.
Contained By:
Dissertation Abstracts International62-11B.
標題:
Engineering, Electronics and Electrical. -
電子資源:
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3033896
ISBN:
0493469621
Low-voltage high-speed switched capacitor circuit design.
Wang, Lei.
Low-voltage high-speed switched capacitor circuit design.
- 81 p.
Chair: S. H. K. Embabi.
Thesis (Ph.D.)--Texas A&M University, 2001.
New methods were studied for the purpose of designing low voltage and high speed switched capacitor (SC) circuits without using the on-chip voltage bootstrapper. Auto-zeroed integrator (AZI) was proposed as the fundamental building block of low voltage SC systems. AZI has no signal dependent switches, so it can work at the low voltage with a high operating speed. Also, AZI is not sensitive to the charge injection and non-linear resistance related distortions. The low voltage two-stage fully differential opamp built for the AZI has a dynamic common-mode feedback circuit without signal dependent switches. Three testing circuits using AZI were implemented in 1.2μm CMOS process at 1.5V power supply voltage.
ISBN: 0493469621Subjects--Topical Terms:
626636
Engineering, Electronics and Electrical.
Low-voltage high-speed switched capacitor circuit design.
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81 p.
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Chair: S. H. K. Embabi.
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Thesis (Ph.D.)--Texas A&M University, 2001.
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New methods were studied for the purpose of designing low voltage and high speed switched capacitor (SC) circuits without using the on-chip voltage bootstrapper. Auto-zeroed integrator (AZI) was proposed as the fundamental building block of low voltage SC systems. AZI has no signal dependent switches, so it can work at the low voltage with a high operating speed. Also, AZI is not sensitive to the charge injection and non-linear resistance related distortions. The low voltage two-stage fully differential opamp built for the AZI has a dynamic common-mode feedback circuit without signal dependent switches. Three testing circuits using AZI were implemented in 1.2μm CMOS process at 1.5V power supply voltage.
520
$a
The first testing circuit is a second order fully differential SC bandpass filter working at 5.0MHz sampling rate. The central frequency of the filter was designed at 833KHz and the Q factor is 8. The second testing circuit is a fourth order fully differential SC bandpass delta-sigma modulator with the sampling rate of 5.0MHz too. It has a narrowband of 25KHz centered at the intermediate frequency (IF) of 1.25MHz. The tested results demonstrated a 61dB signal-to-noise-and-distortion-ratio (SNDR) and a −78dBc third order inter-modulation (IM3).
520
$a
The third circuit is a 2-path fully differential fourth order bandpass delta-sigma modulator. It has an effective sampling rate of 10MHz double of the clock rate of 5.0MZ. The signal narrowband of the 2-path modulator is then located at 2.5MHz. The tested results are: 65 dB SNDR, −75dBc IM3, and a −35dBc spurious image of the desired signal.
520
$a
As a supporting and extending research of SC circuits, a new architecture of the SC differentiator having less sensitivity to mismatch and lower thermal noise was also mentioned. A 2-path fourth order SC delta-sigma modulator working at 3.0V supply voltage and 60MHz sampling rate was designed and implemented in 0.35μm CMOS process. The measured maximal SNR is 76dB for 0.25V (peak differential) sine wave input.
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School code: 0803.
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