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Deadlock recovery-based router archi...

Choi, Yungho.

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Deadlock recovery-based router architectures for high performance networks.

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Deadlock recovery-based router architectures for high performance networks./
Author:	Choi, Yungho.
Description:	188 p.
Notes:	Adviser: Timothy M. Pinkston.
Contained By:	Dissertation Abstracts International63-05B.
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3054723
ISBN:	0493699384

Deadlock recovery-based router architectures for high performance networks.
Choi, Yungho.

Deadlock recovery-based router architectures for high performance networks. - 188 p.

Adviser: Timothy M. Pinkston.

Thesis (Ph.D.)--University of Southern California, 2001.

Multiprocessor systems have been developed to efficiently solve complex and large scientific problems. Generally, these systems have a critical component, i.e., interconnection network, which significantly affects system performance by determining the communication capability of multiprocessor systems. In recent years, with the emergence of bandwidth-hungry applications and multi-GHz processors, the demand on high performance interconnection networks has been increased to meet rapidly growing communication needs of multiprocessor systems.

ISBN: 0493699384Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Deadlock recovery-based router architectures for high performance networks.
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035 $a (UnM)AAI3054723
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100 1 $a Choi, Yungho. $3 1256067
245 1 0 $a Deadlock recovery-based router architectures for high performance networks.
300 $a 188 p.
500 $a Adviser: Timothy M. Pinkston.
500 $a Source: Dissertation Abstracts International, Volume: 63-05, Section: B, page: 2502.
502 $a Thesis (Ph.D.)--University of Southern California, 2001.
520 $a Multiprocessor systems have been developed to efficiently solve complex and large scientific problems. Generally, these systems have a critical component, i.e., interconnection network, which significantly affects system performance by determining the communication capability of multiprocessor systems. In recent years, with the emergence of bandwidth-hungry applications and multi-GHz processors, the demand on high performance interconnection networks has been increased to meet rapidly growing communication needs of multiprocessor systems.
520 $a To satisfy this demand, routing algorithms must fully utilize network resources while efficiently handling message deadlock which leads to the halting of an entire system. There are largely two classes of routing algorithms according to the way deadlocks can be dealt: deadlock avoidance-based and deadlock recovery-based routing algorithms. Deadlock avoidance-based networks prevent deadlocks by enforcing routing restrictions, which hampers routing adaptivity and, therefore, limits network performance. To overcome this problem, recently a number of deadlock recovery-based networks have been proposed, which maximize routing adaptivity and, thus, significantly increase network performance. But, the increased routing adaptivity could lead to slower and more complicated router architectures, degrading overall network performance.
520 $a In order to minimize the architecture complexity of deadlock recovery-based routers and to maximize network performance, this dissertation optimizes deadlock recovery-based router architectures by proposing two router component design solutions, i.e., partitioned crossbar designs and enhanced dynamically allocated multi-queue designs. These solutions significantly reduce the architecture complexity of deadlock recovery-based routers while fully benefiting from their capability, leading to optimal deadlock recovery-based router architectures.
520 $a Through extensive evaluations of various router architectures, this dissertation verifies that the true fully adaptive routing capability of deadlock recovery schemes can be efficiently implemented in routers and, hence, their superior network performance can be realized. Finally, this work demonstrates the feasibility of some of the proposed router architectures by implementing the WARRP router.
590 $a School code: 0208.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 0 $a University of Southern California. $3 700129
773 0 $t Dissertation Abstracts International $g 63-05B.
790 $a 0208
790 1 0 $a Pinkston, Timothy M., $e advisor
791 $a Ph.D.
792 $a 2001
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3054723