東華大學圖書館 |

Language: English

Help

回圖書館首頁

手機版館藏查詢

Back

Switch To: Labeled | MARC Mode | ISBD

Architecture and simulation of selec...

University of Southern California.

Linked to FindBook

Google Book

Amazon

博客來

Architecture and simulation of selected fine-grained VLSI array processors.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Architecture and simulation of selected fine-grained VLSI array processors./
Author:	Wu, Tony Hung-Yao.
Description:	132 p.
Notes:	Adviser: Bing J. Sheu.
Contained By:	Dissertation Abstracts International57-03B.
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=9621733

Architecture and simulation of selected fine-grained VLSI array processors.
Wu, Tony Hung-Yao.

Architecture and simulation of selected fine-grained VLSI array processors. - 132 p.

Adviser: Bing J. Sheu.

Thesis (Ph.D.)--University of Southern California, 1995.

With rapid advances of semiconductor manufacturing technologies and the mature computer-aided design tools, the trend of moving from serial signal processing to parallel processing follows a natural progress. The constraint on VLSI implementation in circuit complexity can be alleviated by the use of regular, repetitive architectural structures. Scalability and massive parallelism provide the enormous throughput rate and processing capability that conventional sequential processors cannot achieve.Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Architecture and simulation of selected fine-grained VLSI array processors.
LDR:03442nmm 2200301 a 45 001 886459
005 20101007
008 101007s1995 ||||||||||||||||| ||eng d
035 $a (UMI)AAI9621733
035 $a AAI9621733
040 $a UMI $c UMI
100 1 $a Wu, Tony Hung-Yao. $3 1058156
245 1 0 $a Architecture and simulation of selected fine-grained VLSI array processors.
300 $a 132 p.
500 $a Adviser: Bing J. Sheu.
500 $a Source: Dissertation Abstracts International, Volume: 57-03, Section: B, page: 2049.
502 $a Thesis (Ph.D.)--University of Southern California, 1995.
520 $a With rapid advances of semiconductor manufacturing technologies and the mature computer-aided design tools, the trend of moving from serial signal processing to parallel processing follows a natural progress. The constraint on VLSI implementation in circuit complexity can be alleviated by the use of regular, repetitive architectural structures. Scalability and massive parallelism provide the enormous throughput rate and processing capability that conventional sequential processors cannot achieve.
520 $a An analog compact neural network model is reviewed. It is a powerful parallel processing paradigm consisting of densely-connected analog computing cells. Various applications, such as edge detection, hole-filling, and connected-component detection, can be accomplished by changing the local interconnection strengths, which are programmed through the coefficient templates.
520 $a The behavioral simulator cnna, which reads in the configuration information and simulates the dynamic behavior of the network, is presented. A unique feature of this simulator is the hardware annealing capability which provides an efficient method of finding globally optimal solutions. Effects of hardware annealing and the different bias setting are presented. Performance comparisons with respect to image sizes, and template sizes have been summarized. A comparison with simulators developed by other researchers has also been included.
520 $a The parallel computation architecture is defined. A compiler and its associated programming language greatly facilitate the simulation of compact neural networks in order to optimize the design parameters. The framework of the whole simulation environment is also presented.
520 $a An innovative architectural mapping based on the multiplication-accumulation techniques which is similar to distributed arithmetic is described. The array processor is most suitable for high performance requirement of 2-dimensional forward and inverse discrete cosine transformation tasks. Each computing cell contains two adders: one for 2-bit multiplication and the other one for partial-sum accumulation. The computation power could reach 10 giga-operations-per-second at a system clock 100 MHz by using a 0.5 $\mu $m CMOS manufacturing technology. The accuracy tests of the inverse discrete cosine transformation have been verified and comparison with other researchers' work is summarized. These accomplished results lay a critical foundation for the increasingly important multimedia applications, especially in image, video, and speech processing.
590 $a School code: 0208.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 $a University of Southern California. $3 700129
773 0 $t Dissertation Abstracts International $g 57-03B.
790 $a 0208
790 1 0 $a Sheu, Bing J., $e advisor
791 $a Ph.D.
792 $a 1995
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=9621733