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Predictive technology modeling for s...

Arizona State University.

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Predictive technology modeling for scaled CMOS.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Predictive technology modeling for scaled CMOS./
Author:	Zhao, Wei.
Description:	96 p.
Notes:	Source: Dissertation Abstracts International, Volume: 70-04, Section: B, page: 2494.
Contained By:	Dissertation Abstracts International70-04B.
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3353697
ISBN:	9781109102949

Predictive technology modeling for scaled CMOS.
Zhao, Wei.

Predictive technology modeling for scaled CMOS. - 96 p.

Source: Dissertation Abstracts International, Volume: 70-04, Section: B, page: 2494.

Thesis (Ph.D.)--Arizona State University, 2009.

Predictive technology models (PTMs) are critical for early circuit design research. To accurately predict the characteristics of a front-end-of-the-line (FEOL) nanoscale complementary metal--oxide--semiconductor (CMOS), emerging physical effects such as process variations and correlations among model parameters, must be included. In this work, new generation of predictive models are developed for 250nm to 32nm technology nodes to accomplish these goals. The accuracy of PTMs is comprehensively verified: the error of on-current is below 10%. By tuning only ten primary parameters, PTMs can be easily customized to cover a wide range of process uncertainties.

ISBN: 9781109102949Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Predictive technology modeling for scaled CMOS.
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020 $a 9781109102949
035 $a (UMI)AAI3353697
035 $a AAI3353697
040 $a UMI $c UMI
100 1 $a Zhao, Wei. $3 893199
245 1 0 $a Predictive technology modeling for scaled CMOS.
300 $a 96 p.
500 $a Source: Dissertation Abstracts International, Volume: 70-04, Section: B, page: 2494.
502 $a Thesis (Ph.D.)--Arizona State University, 2009.
520 $a Predictive technology models (PTMs) are critical for early circuit design research. To accurately predict the characteristics of a front-end-of-the-line (FEOL) nanoscale complementary metal--oxide--semiconductor (CMOS), emerging physical effects such as process variations and correlations among model parameters, must be included. In this work, new generation of predictive models are developed for 250nm to 32nm technology nodes to accomplish these goals. The accuracy of PTMs is comprehensively verified: the error of on-current is below 10%. By tuning only ten primary parameters, PTMs can be easily customized to cover a wide range of process uncertainties.
520 $a Process variation becomes increasingly important as the feature dimensions of complementary metal--oxide--semiconductor (CMOS) technology continue to shrink. As a result, statistical circuit analysis and optimization are also critical. Primary process variation sources need to be identified and modeled for further circuit simulation. Based on the knowledge from developing predictive models, a rigorous method to extract process variations from in-situ current versus voltage measurements is proposed. Transistor statistics are collected from a test chip fabricated in a 65nm process. Effective channel length, threshold voltage and mobility are recognized as the leading variation sources, due to the tremendous process challenges in lithography, channel doping, and stress. To decompose these variations, three critical current versus voltage points from the leakage and linear regions are identified. The extracted effective channel length, threshold voltage and mobility variations are then normally distributed with negligible spatial correlation. By including the extracted variations in the nominal model file, accurate predictions of the change of drive current in all operation regions and process corners are achieved. Back-end-of-the-line (BEOL) interconnects becomes a limiting factor in circuit performance as complementary metal--oxide--semiconductor (CMOS) technology scales. To efficiently extract the paratactic of interconnects, a compact capacitance model is developed. Physical models for interconnect are also proposed for major structures: line-to-ground, parallel lines above a plane and wires between two planes. By analyzing the electrical field distribution, the capacitance model agrees well with numerical simulation in a wide range of metal dimensions. This capacitance model provides a solid base for evaluating the impact of interconnects.
590 $a School code: 0010.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 $a Arizona State University. $3 1017445
773 0 $t Dissertation Abstracts International $g 70-04B.
790 $a 0010
791 $a Ph.D.
792 $a 2009
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3353697