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Algorithmic techniques for nanometer...

Texas A&M University.

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Algorithmic techniques for nanometer VLSI design and manufacturing closure.

Record Type:	Language materials, printed : Monograph/item
Title/Author:	Algorithmic techniques for nanometer VLSI design and manufacturing closure./
Author:	Hu, Shiyan.
Description:	162 p.
Notes:	Adviser: Jiang Hu.
Contained By:	Dissertation Abstracts International69-07B.
Subject:	Engineering, Electronics and Electrical. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3321706
ISBN:	9780549721055

Algorithmic techniques for nanometer VLSI design and manufacturing closure.
Hu, Shiyan.

Algorithmic techniques for nanometer VLSI design and manufacturing closure. - 162 p.

Adviser: Jiang Hu.

Thesis (Ph.D.)--Texas A&M University, 2008.

As Very Large Scale Integration (VLSI) technology moves to the nanoscale regime, design and manufacturing closure becomes very difficult to achieve due to increasing chip and power density. Imperfections due to process, voltage and temperature variations aggravate the problem. Uncertainty in electrical characteristic of individual device and wire may cause significant performance deviations or even functional failures. These impose tremendous challenges to the continuation of Moore's law as well as the growth of semiconductor industry.

ISBN: 9780549721055Subjects--Topical Terms:

626636
Engineering, Electronics and Electrical.

Algorithmic techniques for nanometer VLSI design and manufacturing closure.
LDR:03407nam 2200325 a 45 001 855603
005 20100708
008 100708s2008 ||||||||||||||||| ||eng d
020 $a 9780549721055
035 $a (UMI)AAI3321706
035 $a AAI3321706
040 $a UMI $c UMI
100 1 $a Hu, Shiyan. $3 1022240
245 1 0 $a Algorithmic techniques for nanometer VLSI design and manufacturing closure.
300 $a 162 p.
500 $a Adviser: Jiang Hu.
500 $a Source: Dissertation Abstracts International, Volume: 69-07, Section: B, page: 4331.
502 $a Thesis (Ph.D.)--Texas A&M University, 2008.
520 $a As Very Large Scale Integration (VLSI) technology moves to the nanoscale regime, design and manufacturing closure becomes very difficult to achieve due to increasing chip and power density. Imperfections due to process, voltage and temperature variations aggravate the problem. Uncertainty in electrical characteristic of individual device and wire may cause significant performance deviations or even functional failures. These impose tremendous challenges to the continuation of Moore's law as well as the growth of semiconductor industry.
520 $a Efforts are needed in both deterministic design stage and variation-aware design stage. This research proposes various innovative algorithms to address both stages for obtaining a design with high frequency, low power and high robustness. For deterministic optimizations, new buffer insertion and gate sizing techniques are proposed. For variation-aware optimizations, new lithography-driven and post-silicon tuning-driven design techniques are proposed.
520 $a For buffer insertion, a new slew buffering formulation is presented and is proved to be NP-hard. Despite this, a highly efficient algorithm which runs > 90x faster than the best alternatives is proposed. The algorithm is also extended to handle continuous buffer locations and blockages.
520 $a For gate sizing, a new algorithm is proposed to handle discrete gate library in contrast to unrealistic continuous gate library assumed by most existing algorithms. Our approach is a continuous solution guided dynamic programming approach, which integrates the high solution quality of dynamic programming with the short runtime of rounding continuous solution.
520 $a For lithography-driven optimization, the problem of cell placement considering manufacturability is studied. Three algorithms are proposed to handle cell flipping and relocation. They are based on dynamic programming and graph theoretic approaches, and can provide different tradeoff between variation reduction and wire-length increase.
520 $a For post-silicon tuning-driven optimization, the problem of unified adaptivity optimization on logical and clock signal tuning is studied, which enables us to significantly save resources. The new algorithm is based on a novel linear programming formulation which is solved by an advanced robust linear programming technique. The continuous solution is then discretized using binary search accelerated dynamic programming, batch based optimization, and Latin Hypercube sampling based fast simulation.
590 $a School code: 0803.
650 4 $a Engineering, Electronics and Electrical. $3 626636
690 $a 0544
710 2 $a Texas A&M University. $3 718977
773 0 $t Dissertation Abstracts International $g 69-07B.
790 $a 0803
790 1 0 $a Hu, Jiang, $e advisor
791 $a Ph.D.
792 $a 2008
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3321706