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Generating Hardware Assertion Checke...
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Zilic, Zeljko.
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Generating Hardware Assertion Checkers = For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring /
紀錄類型:
書目-語言資料,印刷品 : Monograph/item
正題名/作者:
Generating Hardware Assertion Checkers/ by Marc Boule, Zeljko Zilic.
其他題名:
For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring /
作者:
Boule, Marc.
其他作者:
Zilic, Zeljko.
出版者:
Dordrecht :Springer Science + Business Media B.V, : 2008.,
面頁冊數:
280 p. :ill., digital ;24 cm.
Contained By:
Springer eBooks
標題:
Integrated circuits - Verification. -
電子資源:
http://dx.doi.org/10.1007/978-1-4020-8586-4http://dx.doi.org/10.1007/978-1-4020-8586-4
ISBN:
9781402085857 (paper)
Generating Hardware Assertion Checkers = For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring /
Boule, Marc.
Generating Hardware Assertion Checkers
For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring /[electronic resource] :by Marc Boule, Zeljko Zilic. - Dordrecht :Springer Science + Business Media B.V,2008. - 280 p. :ill., digital ;24 cm.
ISBN: 9781402085857 (paper)Subjects--Topical Terms:
827163
Integrated circuits
--Verification.
LC Class. No.: TK7874.75 / .F67 1997
Dewey Class. No.: 621.395
Generating Hardware Assertion Checkers = For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring /
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