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Closing the gap between ASIC & custo...

Keutzer, Kurt William, (1955-)

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Closing the gap between ASIC & custom = tools and techniques for high-performance ASIC design /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Closing the gap between ASIC & custom/ David Chinnery, Kurt Keutzer.
其他題名:	tools and techniques for high-performance ASIC design /
作者:	Chinnery, David.
其他作者:	Keutzer, Kurt William,
出版者:	Boston :Kluwer Academic Publishers, : 2002.,
面頁冊數:	xiv, 407 p. :ill. ;25 cm.
標題:	Application specific integrated circuits. -
電子資源:	http://www.netLibrary.com/urlapi.asp?action=summary&v=1&bookid=99306An electronic book accessible through the World Wide Web; click for information
ISBN:	0306478234 (electronic bk.)

Closing the gap between ASIC & custom = tools and techniques for high-performance ASIC design /
Chinnery, David.

Closing the gap between ASIC & customtools and techniques for high-performance ASIC design /[electronic resource] :David Chinnery, Kurt Keutzer. - Boston :Kluwer Academic Publishers,2002. - xiv, 407 p. :ill. ;25 cm.

Includes bibliographical references.

Introduction and overview of the book /David Chinnery, Kurt Keutzer --Contributing factors --

Electronic reproduction.
Boulder, Colo. :
NetLibrary,
2004.

Available via World Wide Web.

ISBN: 0306478234 (electronic bk.)Subjects--Topical Terms:

590062
Application specific integrated circuits.
Index Terms--Genre/Form:

542853
Electronic books.

LC Class. No.: TK7874.6 / .C47 2002eb

Dewey Class. No.: 621.3815

Closing the gap between ASIC & custom = tools and techniques for high-performance ASIC design /
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245 1 0 $a Closing the gap between ASIC & custom $h [electronic resource] : $b tools and techniques for high-performance ASIC design / $c David Chinnery, Kurt Keutzer.
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300 $a xiv, 407 p. : $b ill. ; $c 25 cm.
504 $a Includes bibliographical references.
505 0 0 $t Introduction and overview of the book / $r David Chinnery, Kurt Keutzer -- $g Contributing factors -- $t Improving perfomance through microarchitecture / $r David Chinnery, Kurt Keutzer -- $t Reducing the timing overhead/ $r David Chinnery, Kurt Keutzer -- $t High-speed logic, circuits, libraries and layout / $r Andrew Chang ... [et al.] -- $t Finding peak performance in a process/ $r David Chinnery, Kurt Keutzer -- $g Design techniques -- $t Physical prototyping plans for high performance / $r Michel Courtoy ... [et al.] -- $t Automatic replacement of flip-flops by latches in ASICs/ $r David Chinnery ... [et al.] -- $t Useful-skew clock synthesis boosts ASIC performance / $r Wayne Dai, David Staepelaere -- $t Faster and lower power cell-based designs with transistor-level cell sizing/ $r Michel C緌t歋, Philippe Hurat -- $t Design optimization with automated flex-cell creation / $r Debashis Bhattacharya, Vamsi Boppana -- $t Exploiting structure and managing wires to increase density and performance/ $r Andrew Chang, William J. Dally -- $t Semi-custom methods in a high-performance microprocessor design / $r Gregory A. Northrop -- $t Controlling uncertainty in high frequency designs/ $r Stephen E. Rich, Mathhew J. Parker, Jim Schwartz -- $t Increasing circuit performance through statistical design techniques / $r Michael Orshansky -- $g Design examples -- $t Achieving 550MHz in a standard cell ASIC methodology/ $r David Chinnery, Borivoje Nikoli歊, Kurt Keutzer -- $t iCORE 520MHz synthesizable CPU core / $r Nick Richardson ... [et al.] -- $t Creating synthesizable ARM processors with near custom performance / $r David Flynn, Michael Keating.
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