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4H-SiC Power MOSFETs Design and Reliability.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	4H-SiC Power MOSFETs Design and Reliability./
作者:	Zhu, Shengnan.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2023,
面頁冊數:	189 p.
附註:	Source: Dissertations Abstracts International, Volume: 85-04, Section: B.
Contained By:	Dissertations Abstracts International85-04B.
標題:	Engineering. -
電子資源:	https://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=30782397
ISBN:	9798380589260

4H-SiC Power MOSFETs Design and Reliability.
Zhu, Shengnan.

4H-SiC Power MOSFETs Design and Reliability. - Ann Arbor : ProQuest Dissertations & Theses, 2023 - 189 p.

Source: Dissertations Abstracts International, Volume: 85-04, Section: B.

Thesis (Ph.D.)--The Ohio State University, 2023.

The adoption of 4H-SiC power MOSFETs in automotive applications is on the rise, driven primarily by performance and reliability improvements. This dissertation presents eleven 650 V SiC power MOSFET designs, which have been fabricated by X-Fab on two 6-in SiC wafers and packaged for characterization. We evaluate the effects of the JFET region and layout topology designs on the static and dynamic performance and reliability of the 650 V SiC power MOSFETs. In addition, research work on gate oxide reliability, including gate leakage current and gate oxide lifetime prediction, is also conducted for commercially available planar and trench SiC power MOSFETs from various vendors.The JFET region design variation used in the 650 V SiC power MOSFETs includes variations in JFET width and doping concentration. Packaged devices undergo typical I-V and C-V characterizations and double-pulse tests. Results prove that a narrow JFET region with increased JFET doping concentration achieves low specific ON-resistance (Ron,sp) and reduced gate-drain capacitance (Cgd). Off-state TCAD simulation and short-circuit measurements demonstrate that a smaller JFET region benefits the device reliability by better shielding the gate oxide during high-temperature reverse bias (HTRB) stress and increases the short-circuit withstand time (SCWT).We propose a new cell topology (Dodecagonal cell, or Dod cell for short) for planar SiC MOSFETs. The Dod cell structure features a twelve-sided P+ region with an ohmic contact located on the top, surrounded by six hexagonal poly-Si gate regions that are connected by poly-Si bars. The hexagonal JFET regions are placed inside the gate regions. Similar to the previously proposed Octogonal (Oct) cell, the Dod cell is designed with minimum JFET regions to achieve low Cgd and is suitable for high-frequency switching conditions. Compared with the Oct cell, the new Dod cell reduces the Ron,sp by optimizing the geometry, resulting in improved static performance. To design the 650 V SiC power MOSFETs, we use five cell topologies: Dod, Oct, Linear, Orthogonal P+, and hexagonal cells. The Linear, Orthogonal P+, and hexagonal cells are also applied with cell pitch variations. We found that the hexagonal cell with a small cell pitch obtains the lowest Ron,sp, which is recommended for applications requiring high power and current, such as electric vehicles (EVs).Distinct leakage current behavior under various constant gate biases is observed and categorized into three types. Under a high oxide field (>9MV/cm), hole generation and trapping occur. Under low oxide fields (<9MV/cm), electron trapping dominates. The hole and electron trapping mechanisms are validated by the change in threshold voltage during the constant gate voltage stress. Due to hole generation and trapping, constant-voltage time-dependent dielectric breakdown (TDDB) results show an accelerated gate oxide failure, leading to an overestimation of the gate oxide lifetime under normal operating conditions. Therefore, it is recommended that constant-voltage TDDB measurements and device screening be conducted with lower gate voltages (< 9 MV/cm) to avoid hole generation and trapping caused by the impact ionization and/or anode hole injection (AHI).Additionally, we conducted constant-voltage TDDB measurements on commercially available SiC power MOSFETs from various vendors to evaluate the gate oxide lifetime. The asymmetric trench MOSFETs, benefiting from the thick gate oxide, exhibited three orders of magnitude higher gate oxide lifetime than the other measured devices under operational voltage. A recently proposed charge-to-breakdown approach, which is less time-consuming than the constant-voltage TDDB measurements, is used on commercial SiC power MOSFETs to predict the oxide lifetime. The approach is less conservative than the constant-voltage TDDB method and needs further investigation.

ISBN: 9798380589260Subjects--Topical Terms:

586835
Engineering.
Subjects--Index Terms:

SiC power MOSFETs

4H-SiC Power MOSFETs Design and Reliability.
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300 $a 189 p.
500 $a Source: Dissertations Abstracts International, Volume: 85-04, Section: B.
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502 $a Thesis (Ph.D.)--The Ohio State University, 2023.
520 $a The adoption of 4H-SiC power MOSFETs in automotive applications is on the rise, driven primarily by performance and reliability improvements. This dissertation presents eleven 650 V SiC power MOSFET designs, which have been fabricated by X-Fab on two 6-in SiC wafers and packaged for characterization. We evaluate the effects of the JFET region and layout topology designs on the static and dynamic performance and reliability of the 650 V SiC power MOSFETs. In addition, research work on gate oxide reliability, including gate leakage current and gate oxide lifetime prediction, is also conducted for commercially available planar and trench SiC power MOSFETs from various vendors.The JFET region design variation used in the 650 V SiC power MOSFETs includes variations in JFET width and doping concentration. Packaged devices undergo typical I-V and C-V characterizations and double-pulse tests. Results prove that a narrow JFET region with increased JFET doping concentration achieves low specific ON-resistance (Ron,sp) and reduced gate-drain capacitance (Cgd). Off-state TCAD simulation and short-circuit measurements demonstrate that a smaller JFET region benefits the device reliability by better shielding the gate oxide during high-temperature reverse bias (HTRB) stress and increases the short-circuit withstand time (SCWT).We propose a new cell topology (Dodecagonal cell, or Dod cell for short) for planar SiC MOSFETs. The Dod cell structure features a twelve-sided P+ region with an ohmic contact located on the top, surrounded by six hexagonal poly-Si gate regions that are connected by poly-Si bars. The hexagonal JFET regions are placed inside the gate regions. Similar to the previously proposed Octogonal (Oct) cell, the Dod cell is designed with minimum JFET regions to achieve low Cgd and is suitable for high-frequency switching conditions. Compared with the Oct cell, the new Dod cell reduces the Ron,sp by optimizing the geometry, resulting in improved static performance. To design the 650 V SiC power MOSFETs, we use five cell topologies: Dod, Oct, Linear, Orthogonal P+, and hexagonal cells. The Linear, Orthogonal P+, and hexagonal cells are also applied with cell pitch variations. We found that the hexagonal cell with a small cell pitch obtains the lowest Ron,sp, which is recommended for applications requiring high power and current, such as electric vehicles (EVs).Distinct leakage current behavior under various constant gate biases is observed and categorized into three types. Under a high oxide field (>9MV/cm), hole generation and trapping occur. Under low oxide fields (<9MV/cm), electron trapping dominates. The hole and electron trapping mechanisms are validated by the change in threshold voltage during the constant gate voltage stress. Due to hole generation and trapping, constant-voltage time-dependent dielectric breakdown (TDDB) results show an accelerated gate oxide failure, leading to an overestimation of the gate oxide lifetime under normal operating conditions. Therefore, it is recommended that constant-voltage TDDB measurements and device screening be conducted with lower gate voltages (< 9 MV/cm) to avoid hole generation and trapping caused by the impact ionization and/or anode hole injection (AHI).Additionally, we conducted constant-voltage TDDB measurements on commercially available SiC power MOSFETs from various vendors to evaluate the gate oxide lifetime. The asymmetric trench MOSFETs, benefiting from the thick gate oxide, exhibited three orders of magnitude higher gate oxide lifetime than the other measured devices under operational voltage. A recently proposed charge-to-breakdown approach, which is less time-consuming than the constant-voltage TDDB measurements, is used on commercial SiC power MOSFETs to predict the oxide lifetime. The approach is less conservative than the constant-voltage TDDB method and needs further investigation.
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650 4 $a Electrical engineering. $3 649834
650 4 $a Solid state physics. $3 518873
650 4 $a Computer engineering. $3 621879
653 $a SiC power MOSFETs
653 $a MOSFET designs
653 $a Reliability
653 $a JFET region design
653 $a Cell topology
653 $a Gate oxide reliability
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710 2 $a The Ohio State University. $b Electrical and Computer Engineering. $3 1672495
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