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Nanoscale Device Design: A TCAD Anal...

Totorica, Nathan.

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Nanoscale Device Design: A TCAD Analysis of 2nm GAAFET Nanosheet.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Nanoscale Device Design: A TCAD Analysis of 2nm GAAFET Nanosheet./
Author:	Totorica, Nathan.
Published:	Ann Arbor : ProQuest Dissertations & Theses, : 2024,
Description:	43 p.
Notes:	Source: Masters Abstracts International, Volume: 85-11.
Contained By:	Masters Abstracts International85-11.
Subject:	Engineering. -
Online resource:	https://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=31238349
ISBN:	9798382732558

Nanoscale Device Design: A TCAD Analysis of 2nm GAAFET Nanosheet.
Totorica, Nathan.

Nanoscale Device Design: A TCAD Analysis of 2nm GAAFET Nanosheet. - Ann Arbor : ProQuest Dissertations & Theses, 2024 - 43 p.

Source: Masters Abstracts International, Volume: 85-11.

Thesis (M.S.)--University of Idaho, 2024.

The size of field effect transistors used in CMOS integrated circuits shrinks over each technology node to achieve lower power consumption, higher performance, and higher density. The increase in electrostatic control and reduced short channel effects (SCE) are key benefits to adopting new architectures like Gate-All-Around FET (GAAFET) to meet scaling requirements for next generation process nodes. Advanced architectures in the nanometer regime bring unique design challenges that require thorough characterization of device performance to ensure a successful and robust implementation. Sentaurus TCAD provides a valuable tool to begin exploring the many design choices faced when encountering a novel structure such as GAAFET. Design choices around device geometries and materials can be simulated to understand impacts on performance. In this work, several of these design choices are explored, such as channel geometry, vertical channel stacking, and spacer material options, all while using the projected parameters of the 2nm node. Key device metrics like transfer characteristics, SCE, extension resistance, and gate capacitances are used to create a basis for evaluating the design health. The devices designed using TCAD are then simulated at the circuit level to further explore tradeoffs and provide additional figure of merits into device performance.

ISBN: 9798382732558Subjects--Topical Terms:

586835
Engineering.
Subjects--Index Terms:

Gate-All-Around FET

Nanoscale Device Design: A TCAD Analysis of 2nm GAAFET Nanosheet.
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245 1 0 $a Nanoscale Device Design: A TCAD Analysis of 2nm GAAFET Nanosheet.
260 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2024
300 $a 43 p.
500 $a Source: Masters Abstracts International, Volume: 85-11.
500 $a Advisor: Li, Feng.
502 $a Thesis (M.S.)--University of Idaho, 2024.
520 $a The size of field effect transistors used in CMOS integrated circuits shrinks over each technology node to achieve lower power consumption, higher performance, and higher density. The increase in electrostatic control and reduced short channel effects (SCE) are key benefits to adopting new architectures like Gate-All-Around FET (GAAFET) to meet scaling requirements for next generation process nodes. Advanced architectures in the nanometer regime bring unique design challenges that require thorough characterization of device performance to ensure a successful and robust implementation. Sentaurus TCAD provides a valuable tool to begin exploring the many design choices faced when encountering a novel structure such as GAAFET. Design choices around device geometries and materials can be simulated to understand impacts on performance. In this work, several of these design choices are explored, such as channel geometry, vertical channel stacking, and spacer material options, all while using the projected parameters of the 2nm node. Key device metrics like transfer characteristics, SCE, extension resistance, and gate capacitances are used to create a basis for evaluating the design health. The devices designed using TCAD are then simulated at the circuit level to further explore tradeoffs and provide additional figure of merits into device performance.
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650 4 $a Engineering. $3 586835
650 4 $a Nanoscience. $3 587832
650 4 $a Applied physics. $3 3343996
650 4 $a Electrical engineering. $3 649834
653 $a Gate-All-Around FET
653 $a Short channel effects
653 $a Electrostatics
653 $a Spacer materials
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690 $a 0565
690 $a 0544
690 $a 0215
710 2 $a University of Idaho. $b Electrical and Computer Engineering. $3 2103966
773 0 $t Masters Abstracts International $g 85-11.
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793 $a English
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