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An Analysis of Short Channel Effects...

Raveendran, Srividya.

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An Analysis of Short Channel Effects in Gate All Around FET Devices, A TCAD Simulation.

Record Type:	Electronic resources : Monograph/item
Title/Author:	An Analysis of Short Channel Effects in Gate All Around FET Devices, A TCAD Simulation./
Author:	Raveendran, Srividya.
Published:	Ann Arbor : ProQuest Dissertations & Theses, : 2023,
Description:	73 p.
Notes:	Source: Masters Abstracts International, Volume: 84-12.
Contained By:	Masters Abstracts International84-12.
Subject:	Electrical engineering. -
Online resource:	https://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=30418263
ISBN:	9798379699185

An Analysis of Short Channel Effects in Gate All Around FET Devices, A TCAD Simulation.
Raveendran, Srividya.

An Analysis of Short Channel Effects in Gate All Around FET Devices, A TCAD Simulation. - Ann Arbor : ProQuest Dissertations & Theses, 2023 - 73 p.

Source: Masters Abstracts International, Volume: 84-12.

Thesis (M.S.)--University of Idaho, 2023.

This item must not be sold to any third party vendors.

The Gate All Around (GAA) Field Effect Transistor (FET) is a type of MOS (Metal Oxide Semiconductor) device that circumvents the problem of the existing FinFET devices and produces effective results on scaling up to 7nm technology node and beyond. The significant benefits of this transistor design are size reduction and increased potential for channel length scaling, which attributes to increased transistor density. However, there are some major challenges, like Short Channel Effects (SCE), which include Subthreshold Slope (SS), Drain Induced Barrier lowering (DIBL), and Gate Induced Drain Leakage (GIDL), that are involved in scaling. This paper mainly focuses on reviewing those challenges by analyzing the TCAD simulation results of two different types of GAA FET devices, Nanosheet (NS) and Nanowire (NW), along with the summary of the effect of the width and radius of NS and NW on the above- mentioned short channel effects. A comparative overview of the impact on a single and stacked device is also discussed.

ISBN: 9798379699185Subjects--Topical Terms:

649834
Electrical engineering.
Subjects--Index Terms:

Short Channel Effects

An Analysis of Short Channel Effects in Gate All Around FET Devices, A TCAD Simulation.
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100 1 $a Raveendran, Srividya. $3 3764979
245 1 3 $a An Analysis of Short Channel Effects in Gate All Around FET Devices, A TCAD Simulation.
260 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2023
300 $a 73 p.
500 $a Source: Masters Abstracts International, Volume: 84-12.
500 $a Advisor: Li, Feng.
502 $a Thesis (M.S.)--University of Idaho, 2023.
506 $a This item must not be sold to any third party vendors.
520 $a The Gate All Around (GAA) Field Effect Transistor (FET) is a type of MOS (Metal Oxide Semiconductor) device that circumvents the problem of the existing FinFET devices and produces effective results on scaling up to 7nm technology node and beyond. The significant benefits of this transistor design are size reduction and increased potential for channel length scaling, which attributes to increased transistor density. However, there are some major challenges, like Short Channel Effects (SCE), which include Subthreshold Slope (SS), Drain Induced Barrier lowering (DIBL), and Gate Induced Drain Leakage (GIDL), that are involved in scaling. This paper mainly focuses on reviewing those challenges by analyzing the TCAD simulation results of two different types of GAA FET devices, Nanosheet (NS) and Nanowire (NW), along with the summary of the effect of the width and radius of NS and NW on the above- mentioned short channel effects. A comparative overview of the impact on a single and stacked device is also discussed.
590 $a School code: 0089.
650 4 $a Electrical engineering. $3 649834
650 4 $a Materials science. $3 543314
650 4 $a Nanoscience. $3 587832
653 $a Short Channel Effects
653 $a FET devices
653 $a Metal Oxide Semiconductor
653 $a Transistor design
653 $a Subthreshold Slope
690 $a 0544
690 $a 0565
690 $a 0794
710 2 $a University of Idaho. $b Electrical and Computer Engineering. $3 2103966
773 0 $t Masters Abstracts International $g 84-12.
790 $a 0089
791 $a M.S.
792 $a 2023
793 $a English
856 4 0 $u https://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=30418263