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Accelerating network functions using reconfigurable hardware = design and validation of high throughput and low latency network functions at the access edge /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Accelerating network functions using reconfigurable hardware/ by Ralf Kundel.
Reminder of title:	design and validation of high throughput and low latency network functions at the access edge /
Author:	Kundel, Ralf.
Published:	Cham :Springer Nature Switzerland : : 2024.,
Description:	xvi, 177 p. :ill. (some col.), digital ;24 cm.
Notes:	"Doctoral Thesis accepted by Technical University of Darmstadt, Darmstadt, Germany."
[NT 15003449]:	Introduction -- Background and State-of-the Art -- Design of QOS-Aware Network Functions -- P4sta: High precision network Function Benchmarking -- Evaluation.
Contained By:	Springer Nature eBook
Subject:	Adaptive computing systems. -
Online resource:	https://doi.org/10.1007/978-3-031-52872-9
ISBN:	9783031528729

Accelerating network functions using reconfigurable hardware = design and validation of high throughput and low latency network functions at the access edge /
Kundel, Ralf.

Accelerating network functions using reconfigurable hardwaredesign and validation of high throughput and low latency network functions at the access edge /[electronic resource] :by Ralf Kundel. - Cham :Springer Nature Switzerland :2024. - xvi, 177 p. :ill. (some col.), digital ;24 cm. - Springer theses,2190-5061. - Springer theses..

"Doctoral Thesis accepted by Technical University of Darmstadt, Darmstadt, Germany."

Introduction -- Background and State-of-the Art -- Design of QOS-Aware Network Functions -- P4sta: High precision network Function Benchmarking -- Evaluation.

This book reports on new concepts and methods to design network functions on programmable hardware to accelerate connectivity. First, it introduces the host bypassing concept for improved integration of hardware accelerators in computer systems operating 5G radio access networks. This novel concept bypassed the system's main memory and established direct connectivity between the accelerator and network interface card. This concept leads to improved throughput and significantly lowered latency jitter compared to existing methods. Second, the book analyzes different programmable hardware technologies for hardware-accelerated Internet subscriber handling, including three P4-programmable platforms and FPGAs. It shows that all the approaches have excellent performance and are suitable for Internet access creation. In turn, it presents a fully-fledged accelerated User Plane Function (UPF) designed upon these concepts and its testing in an end-to-end 5G standalone network. Third, it analyses and demonstrates the usability of Active Queue Management (AQM) algorithms on programmable hardware as an expansion to the access edge. It shows the feasibility of the CoDel AQM algorithm and discusses the challenges and constraints to be considered when limited hardware is used, resulting in significant improvements in the Quality of Service. Furthermore, the P4STA measurement framework is introduced, a network function benchmarking concept combing precise hardware-based time measurement methods with software-based load generation to simultaneously ensure high measurement accuracy and flexibility. Researchers and professionals will find in this book new solutions to improve both fixed and mobile internet access networks, offering an informative and inspiring reading for researchers and professionals involved in building the next generation of access edge networks and underlying technology.

ISBN: 9783031528729

Standard No.: 10.1007/978-3-031-52872-9doiSubjects--Topical Terms:

628890
Adaptive computing systems.

LC Class. No.: QA76.9.A3

Dewey Class. No.: 004

Accelerating network functions using reconfigurable hardware = design and validation of high throughput and low latency network functions at the access edge /
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520 $a This book reports on new concepts and methods to design network functions on programmable hardware to accelerate connectivity. First, it introduces the host bypassing concept for improved integration of hardware accelerators in computer systems operating 5G radio access networks. This novel concept bypassed the system's main memory and established direct connectivity between the accelerator and network interface card. This concept leads to improved throughput and significantly lowered latency jitter compared to existing methods. Second, the book analyzes different programmable hardware technologies for hardware-accelerated Internet subscriber handling, including three P4-programmable platforms and FPGAs. It shows that all the approaches have excellent performance and are suitable for Internet access creation. In turn, it presents a fully-fledged accelerated User Plane Function (UPF) designed upon these concepts and its testing in an end-to-end 5G standalone network. Third, it analyses and demonstrates the usability of Active Queue Management (AQM) algorithms on programmable hardware as an expansion to the access edge. It shows the feasibility of the CoDel AQM algorithm and discusses the challenges and constraints to be considered when limited hardware is used, resulting in significant improvements in the Quality of Service. Furthermore, the P4STA measurement framework is introduced, a network function benchmarking concept combing precise hardware-based time measurement methods with software-based load generation to simultaneously ensure high measurement accuracy and flexibility. Researchers and professionals will find in this book new solutions to improve both fixed and mobile internet access networks, offering an informative and inspiring reading for researchers and professionals involved in building the next generation of access edge networks and underlying technology.
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