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An Energy Efficient EdgeAI Autoencoder for Reinforcement Learning.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	An Energy Efficient EdgeAI Autoencoder for Reinforcement Learning./
作者:	Manjunath, Nitheesh Kumar.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2021,
面頁冊數:	103 p.
附註:	Source: Masters Abstracts International, Volume: 83-03.
Contained By:	Masters Abstracts International83-03.
標題:	Engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=28494398
ISBN:	9798535574264

An Energy Efficient EdgeAI Autoencoder for Reinforcement Learning.
Manjunath, Nitheesh Kumar.

An Energy Efficient EdgeAI Autoencoder for Reinforcement Learning. - Ann Arbor : ProQuest Dissertations & Theses, 2021 - 103 p.

Source: Masters Abstracts International, Volume: 83-03.

Thesis (M.S.)--University of Maryland, Baltimore County, 2021.

This item must not be sold to any third party vendors.

In EdgeAI embedded devices that exploit reinforcement learning (RL), it is essential to reduce the number of actions taken by the agent in the real world and minimize the compute-intensive policies learning process. Convolutional autoencoders (AEs) has demonstrated great improvement for speeding up the policy learning time when attached to the RL agent, by compressing the high dimensional input data into a small latent representation for feeding the RL agent.Despite reducing the policy learning time, AE adds a significant computational and memory complexity to the model which contributes to the increase in the total computation and the model size. In this paper, we propose a model for speeding up the policy learning process of RL agent with the use of AE neural networks, which engages binary and ternary precision to address the high complexity overhead without deteriorating the policy that an RL agent learns.Binary Neural Networks (BNNs) and Ternary Neural Networks (TNNs) compress weights into 1 and 2 bits representations, which result in significant compression of the model size and memory as well as simplifying multiply-accumulate (MAC) operations. We evaluate the performance of our model in three RL environments including DonkeyCar, Miniworld sidewalk, and Miniworld Object Pickup, which emulate various real-world applications with different levels of complexity. With proper hyperparameter optimization and architecture exploration, TNN models achieve near the same average reward, Peak Signal to Noise Ratio (PSNR) and Mean Squared Error (MSE) performance as the full-precision model while reducing the model size by 10x compared to full-precision and 3x compared to BNNs. However, in BNN models the average reward drops up to 12%-25% compared to the full-precision even after increasing its model size by 4x. We designed and implemented a scalable hardware accelerator which is configurable in terms of the number of processing elements (PEs) and memory data width to achieve the best power, performance, and energy efficiency trade-off for EdgeAI embedded devices. The proposed hardware implemented on Artix-7 FPGA dissipates 250 μJ energy while meeting 30 frames per second (FPS) throughput requirements. The hardware is configurable to reach an efficiency of over 1 TOP/J on FPGA implementation. The proposed hardware accelerator is synthesized and placed-and-routed in 14nm FinFET ASIC technology which brings down the power dissipation to 3.9 μJ and maximum throughput of 1,250 FPS. Compared to the state of the art TNN implementations on the same target platform, our hardware is 5x and 4.4x (2.2x if technology scaled) more energy efficient on FPGA and ASIC, respectively.

ISBN: 9798535574264Subjects--Topical Terms:

586835
Engineering.
Subjects--Index Terms:

Energy efficient EdgeAI autoencode

An Energy Efficient EdgeAI Autoencoder for Reinforcement Learning.
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300 $a 103 p.
500 $a Source: Masters Abstracts International, Volume: 83-03.
500 $a Advisor: Mohsenin, Tinoosh.
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506 $a This item must not be sold to any third party vendors.
520 $a In EdgeAI embedded devices that exploit reinforcement learning (RL), it is essential to reduce the number of actions taken by the agent in the real world and minimize the compute-intensive policies learning process. Convolutional autoencoders (AEs) has demonstrated great improvement for speeding up the policy learning time when attached to the RL agent, by compressing the high dimensional input data into a small latent representation for feeding the RL agent.Despite reducing the policy learning time, AE adds a significant computational and memory complexity to the model which contributes to the increase in the total computation and the model size. In this paper, we propose a model for speeding up the policy learning process of RL agent with the use of AE neural networks, which engages binary and ternary precision to address the high complexity overhead without deteriorating the policy that an RL agent learns.Binary Neural Networks (BNNs) and Ternary Neural Networks (TNNs) compress weights into 1 and 2 bits representations, which result in significant compression of the model size and memory as well as simplifying multiply-accumulate (MAC) operations. We evaluate the performance of our model in three RL environments including DonkeyCar, Miniworld sidewalk, and Miniworld Object Pickup, which emulate various real-world applications with different levels of complexity. With proper hyperparameter optimization and architecture exploration, TNN models achieve near the same average reward, Peak Signal to Noise Ratio (PSNR) and Mean Squared Error (MSE) performance as the full-precision model while reducing the model size by 10x compared to full-precision and 3x compared to BNNs. However, in BNN models the average reward drops up to 12%-25% compared to the full-precision even after increasing its model size by 4x. We designed and implemented a scalable hardware accelerator which is configurable in terms of the number of processing elements (PEs) and memory data width to achieve the best power, performance, and energy efficiency trade-off for EdgeAI embedded devices. The proposed hardware implemented on Artix-7 FPGA dissipates 250 μJ energy while meeting 30 frames per second (FPS) throughput requirements. The hardware is configurable to reach an efficiency of over 1 TOP/J on FPGA implementation. The proposed hardware accelerator is synthesized and placed-and-routed in 14nm FinFET ASIC technology which brings down the power dissipation to 3.9 μJ and maximum throughput of 1,250 FPS. Compared to the state of the art TNN implementations on the same target platform, our hardware is 5x and 4.4x (2.2x if technology scaled) more energy efficient on FPGA and ASIC, respectively.
590 $a School code: 0434.
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650 4 $a Design optimization. $3 3681984
650 4 $a Random access memory. $3 623617
650 4 $a Deep learning. $3 3554982
650 4 $a Neural networks. $3 677449
650 4 $a Medical research. $2 bicssc $3 1556686
650 4 $a Energy efficiency. $3 3555643
650 4 $a Algorithms. $3 536374
650 4 $a Energy consumption. $3 631630
650 4 $a Data compression. $3 3681696
650 4 $a Field programmable gate arrays. $3 666370
650 4 $a Artificial intelligence. $3 516317
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653 $a Reinforcement learning
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