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Modeling, Mapping and Programming on an FPGA Emulated In-Memory Computing Architecture.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Modeling, Mapping and Programming on an FPGA Emulated In-Memory Computing Architecture./
Author:	Dervay, Andrew.
Published:	Ann Arbor : ProQuest Dissertations & Theses, : 2021,
Description:	54 p.
Notes:	Source: Masters Abstracts International, Volume: 83-02.
Contained By:	Masters Abstracts International83-02.
Subject:	Computer engineering. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=28498335
ISBN:	9798534669480

Modeling, Mapping and Programming on an FPGA Emulated In-Memory Computing Architecture.
Dervay, Andrew.

Modeling, Mapping and Programming on an FPGA Emulated In-Memory Computing Architecture. - Ann Arbor : ProQuest Dissertations & Theses, 2021 - 54 p.

Source: Masters Abstracts International, Volume: 83-02.

Thesis (M.S.)--State University of New York at Binghamton, 2021.

This item must not be sold to any third party vendors.

With Moore's Law waning and IC manufacturers struggling on the promise to reliably shrink transistor sizes, new processor architectures are required to continue making performance gains. One area of focus is the so-called von Neumann bottleneck which is characterized by processor performance vastly outpacing memory performance. As a result, processors incur relatively large performance penalties and dissipate extra power when accessing cache memory. Researchers have attempted to mitigate this problem by proposing in-memory and near-memory computation architectures. By using auxiliary circuitry to process chunks of data before moving it into processor registers, designers hope to squeeze more performance out of von Neumann architectures.Since custom IC design is expensive and time consuming, this work outlines a modeling framework for behavioral simulation and synthesizable FPGA emulation of the basic in-memory compute logic functionality using commercial off the shelf hardware. The In-Memory Compute Emulator is a synthesizable design targeting the MAX 10 FPGA that can run standalone programs using a custom ISA. The IMC Emu is then programmed with two modified implementations of AES-128 to compare bit-serial and bit-parallel processing. The bit-serial program is able to calculate composite field SBOX faster than bit-parallel while the bit-parallel program excels over the serial at word based computations.

ISBN: 9798534669480Subjects--Topical Terms:

621879
Computer engineering.
Subjects--Index Terms:

The Rijndael Cipher

Modeling, Mapping and Programming on an FPGA Emulated In-Memory Computing Architecture.
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260 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2021
300 $a 54 p.
500 $a Source: Masters Abstracts International, Volume: 83-02.
500 $a Advisor: Zhao, Wenfeng.
502 $a Thesis (M.S.)--State University of New York at Binghamton, 2021.
506 $a This item must not be sold to any third party vendors.
520 $a With Moore's Law waning and IC manufacturers struggling on the promise to reliably shrink transistor sizes, new processor architectures are required to continue making performance gains. One area of focus is the so-called von Neumann bottleneck which is characterized by processor performance vastly outpacing memory performance. As a result, processors incur relatively large performance penalties and dissipate extra power when accessing cache memory. Researchers have attempted to mitigate this problem by proposing in-memory and near-memory computation architectures. By using auxiliary circuitry to process chunks of data before moving it into processor registers, designers hope to squeeze more performance out of von Neumann architectures.Since custom IC design is expensive and time consuming, this work outlines a modeling framework for behavioral simulation and synthesizable FPGA emulation of the basic in-memory compute logic functionality using commercial off the shelf hardware. The In-Memory Compute Emulator is a synthesizable design targeting the MAX 10 FPGA that can run standalone programs using a custom ISA. The IMC Emu is then programmed with two modified implementations of AES-128 to compare bit-serial and bit-parallel processing. The bit-serial program is able to calculate composite field SBOX faster than bit-parallel while the bit-parallel program excels over the serial at word based computations.
590 $a School code: 0792.
650 4 $a Computer engineering. $3 621879
650 4 $a Electrical engineering. $3 649834
650 4 $a Simulation. $3 644748
650 4 $a Behavior. $3 532476
650 4 $a Random access memory. $3 623617
650 4 $a Logic. $3 529544
650 4 $a Circuits. $3 3555093
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653 $a Modeling
653 $a Near-memory computing
653 $a Static random access memory
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690 $a 0544
690 $a 0395
690 $a 0389
710 2 $a State University of New York at Binghamton. $b Electrical and Computer Engineering. $3 3174435
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791 $a M.S.
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793 $a English
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