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System Design and Fabrication Using Monolithic 3d Integration of Heterogeneous Technologies.

Record Type:	Electronic resources : Monograph/item
Title/Author:	System Design and Fabrication Using Monolithic 3d Integration of Heterogeneous Technologies./
Author:	Wu, Tony Fan.
Published:	Ann Arbor : ProQuest Dissertations & Theses, : 2021,
Description:	160 p.
Notes:	Source: Dissertations Abstracts International, Volume: 83-05, Section: B.
Contained By:	Dissertations Abstracts International83-05B.
Subject:	Silicon. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=28688372
ISBN:	9798544204749

System Design and Fabrication Using Monolithic 3d Integration of Heterogeneous Technologies.
Wu, Tony Fan.

System Design and Fabrication Using Monolithic 3d Integration of Heterogeneous Technologies. - Ann Arbor : ProQuest Dissertations & Theses, 2021 - 160 p.

Source: Dissertations Abstracts International, Volume: 83-05, Section: B.

Thesis (Ph.D.)--Stanford University, 2021.

This item must not be sold to any third party vendors.

Monolithic three-dimensional (3D) integration enables heterogeneous technologies to be fabricated vertically on top of each other and connected using short high-density inter-layer vias (e.g., conventional vias used to connect metal interconnects in integrated circuits today). In this thesis, I present three systems using monolithic 3D integration of heterogeneous technologies (silicon CMOS, carbon nanotube field-effect transistors or CNFETs, and resistive RAM or RRAM) targeting various objectives: energy-efficient computing, brain-inspired computing model implementation, and trusted system operation. First, I present an integrated circuit (IC) built through monolithic 3D integration of two heterogeneous technologies: RRAM (for implementing on-chip non-volatile memory) on commercial silicon CMOS (for implementing computing units and static RAM or SRAM). This chip achieves 5.7X lower active energy vs. similar chips using other non-volatile memory technologies (e.g., ferroelectric RAM, Flash) at similar speeds. It also enables fine-grained temporal power gating (i.e., shutdown between active modes) with up to 8 μs transition from active mode to shutdown (up to 5,878X quicker vs. on-chip Flash, a common non-volatile memory technology today), and 200 ns transition from shutdown to active mode. Using this chip, we demonstrate, for the first time, correct system operation when multiple bits are stored in each RRAM cell. This feature can improve the inference accuracy of neural networks vs. using 1 bit per RRAM cell. For example, we demonstrate a 2.3X improvement in inference accuracy for handwritten digit recognition. RRAM is subject to write failures, which can severely limit the lifetime of systems with on-chip RRAM. We overcome this challenge using a combination of resilience techniques. As a result, for example, neural network inference performing handwritten digit recognition can now continuously run on our chip for 10 years without accuracy loss. I present a second monolithic 3D chip, built using CNFETs and RRAM, which implements hyperdimensional (HD) computing (a brain-inspired computing model). It exploits the inherent variations and unique properties of CNFETs and RRAM, as well as error resilience properties of HD computing. This chip (fabricated at Stanford) performs pair-wise classification of 21 European languages with 98% mean accuracy. Using simulations, I show that when such a system is implemented at smaller technology nodes (e.g., 28nm node), it can simultaneously achieve lower energy and faster execution time compared to conventional silicon CMOS approaches (e.g., 7.6X lower energy and 4.6X faster execution time). The third monolithic 3D chip, integrating RRAM on commercial silicon CMOS, achieves trusted system operation despite hardware Trojans -- unauthorized modifications to ICs (e.g., by an untrusted fabrication facility) resulting in incorrect functionality. This chip combines special checker circuits based on the theory of error correcting codes with the (non-volatile) programmability of RRAM to implement a new Trojan Prevention and Detection (TPAD) approach. By emulating hardware Trojans in the chip, I show that above 99% of hardware Trojans can be detected, without any execution time (and clock speed) impact. The area and power overheads of our approach depend on the design implemented. For accelerator designs, area (power) overheads are 27% (9%) and 7.4% (7%) for Lempel-Ziv compression and FFT designs, respectively. For general-purpose processor cores, the area and power overheads can be higher.

ISBN: 9798544204749Subjects--Topical Terms:

669429
Silicon.

System Design and Fabrication Using Monolithic 3d Integration of Heterogeneous Technologies.
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520 $a Monolithic three-dimensional (3D) integration enables heterogeneous technologies to be fabricated vertically on top of each other and connected using short high-density inter-layer vias (e.g., conventional vias used to connect metal interconnects in integrated circuits today). In this thesis, I present three systems using monolithic 3D integration of heterogeneous technologies (silicon CMOS, carbon nanotube field-effect transistors or CNFETs, and resistive RAM or RRAM) targeting various objectives: energy-efficient computing, brain-inspired computing model implementation, and trusted system operation. First, I present an integrated circuit (IC) built through monolithic 3D integration of two heterogeneous technologies: RRAM (for implementing on-chip non-volatile memory) on commercial silicon CMOS (for implementing computing units and static RAM or SRAM). This chip achieves 5.7X lower active energy vs. similar chips using other non-volatile memory technologies (e.g., ferroelectric RAM, Flash) at similar speeds. It also enables fine-grained temporal power gating (i.e., shutdown between active modes) with up to 8 μs transition from active mode to shutdown (up to 5,878X quicker vs. on-chip Flash, a common non-volatile memory technology today), and 200 ns transition from shutdown to active mode. Using this chip, we demonstrate, for the first time, correct system operation when multiple bits are stored in each RRAM cell. This feature can improve the inference accuracy of neural networks vs. using 1 bit per RRAM cell. For example, we demonstrate a 2.3X improvement in inference accuracy for handwritten digit recognition. RRAM is subject to write failures, which can severely limit the lifetime of systems with on-chip RRAM. We overcome this challenge using a combination of resilience techniques. As a result, for example, neural network inference performing handwritten digit recognition can now continuously run on our chip for 10 years without accuracy loss. I present a second monolithic 3D chip, built using CNFETs and RRAM, which implements hyperdimensional (HD) computing (a brain-inspired computing model). It exploits the inherent variations and unique properties of CNFETs and RRAM, as well as error resilience properties of HD computing. This chip (fabricated at Stanford) performs pair-wise classification of 21 European languages with 98% mean accuracy. Using simulations, I show that when such a system is implemented at smaller technology nodes (e.g., 28nm node), it can simultaneously achieve lower energy and faster execution time compared to conventional silicon CMOS approaches (e.g., 7.6X lower energy and 4.6X faster execution time). The third monolithic 3D chip, integrating RRAM on commercial silicon CMOS, achieves trusted system operation despite hardware Trojans -- unauthorized modifications to ICs (e.g., by an untrusted fabrication facility) resulting in incorrect functionality. This chip combines special checker circuits based on the theory of error correcting codes with the (non-volatile) programmability of RRAM to implement a new Trojan Prevention and Detection (TPAD) approach. By emulating hardware Trojans in the chip, I show that above 99% of hardware Trojans can be detected, without any execution time (and clock speed) impact. The area and power overheads of our approach depend on the design implemented. For accelerator designs, area (power) overheads are 27% (9%) and 7.4% (7%) for Lempel-Ziv compression and FFT designs, respectively. For general-purpose processor cores, the area and power overheads can be higher.
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