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Resource efficient LDPC decoders = f...

Chandrasetty, Vikram Arkalgud.

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Resource efficient LDPC decoders = from algorithms to hardware architectures /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Resource efficient LDPC decoders/ Vikram Arkalgud Chandrasetty.
Reminder of title:	from algorithms to hardware architectures /
Author:	Chandrasetty, Vikram Arkalgud.
other author:	Aziz, Sayed Mahfuzul.
Published:	Amsterdam :Academic Press, : 2018.,
Description:	1 online resource.
[NT 15003449]:	1.Introduction 2. Overview of LDPC codes 3. Structure and flexibility of LDPC codes 4. LDPC decoding algorithms 5. LDPC decoder architectures 6. Hardware implementation of LDPC decoder 7. LDPC decoders in multimedia communication References 8. Prospective LDPC applications Appendix-A : Sample C-Programs and MATLAB models for LDPC code construction and simulation Appendix-B : Sample Verilog HDL codes for implementation of fully-parallel LDPC decoder architecture Appendix-C : Sample Verilog HDL codes for implementation of partially-parallel LDPC decoder architecture.
Subject:	Decoders (Electronics) -
Online resource:	https://www.sciencedirect.com/science/book/9780128112557
ISBN:	9780128112564 (electronic bk.)

Resource efficient LDPC decoders = from algorithms to hardware architectures /
Chandrasetty, Vikram Arkalgud.

Resource efficient LDPC decodersfrom algorithms to hardware architectures /[electronic resource] :Vikram Arkalgud Chandrasetty. - Amsterdam :Academic Press,2018. - 1 online resource.

Includes bibliographical references and index.

1.Introduction 2. Overview of LDPC codes 3. Structure and flexibility of LDPC codes 4. LDPC decoding algorithms 5. LDPC decoder architectures 6. Hardware implementation of LDPC decoder 7. LDPC decoders in multimedia communication References 8. Prospective LDPC applications Appendix-A : Sample C-Programs and MATLAB models for LDPC code construction and simulation Appendix-B : Sample Verilog HDL codes for implementation of fully-parallel LDPC decoder architecture Appendix-C : Sample Verilog HDL codes for implementation of partially-parallel LDPC decoder architecture.

ISBN: 9780128112564 (electronic bk.)

Nat. Bib. No.: GBB7M5430bnbSubjects--Topical Terms:

2131098
Decoders (Electronics)
Index Terms--Genre/Form:

542853
Electronic books.

LC Class. No.: TK7872.D37

Dewey Class. No.: 621.38932

Resource efficient LDPC decoders = from algorithms to hardware architectures /
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020 $a 9780128112557 (pbk.)
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100 1 $a Chandrasetty, Vikram Arkalgud. $3 3615107
245 1 0 $a Resource efficient LDPC decoders $h [electronic resource] : $b from algorithms to hardware architectures / $c Vikram Arkalgud Chandrasetty.
260 $a Amsterdam : $b Academic Press, $c 2018.
300 $a 1 online resource.
504 $a Includes bibliographical references and index.
505 0 $a 1.Introduction 2. Overview of LDPC codes 3. Structure and flexibility of LDPC codes 4. LDPC decoding algorithms 5. LDPC decoder architectures 6. Hardware implementation of LDPC decoder 7. LDPC decoders in multimedia communication References 8. Prospective LDPC applications Appendix-A : Sample C-Programs and MATLAB models for LDPC code construction and simulation Appendix-B : Sample Verilog HDL codes for implementation of fully-parallel LDPC decoder architecture Appendix-C : Sample Verilog HDL codes for implementation of partially-parallel LDPC decoder architecture.
650 0 $a Decoders (Electronics) $3 2131098
650 0 $a Digital communications. $3 595692
655 4 $a Electronic books. $2 lcsh $3 542853
700 1 $a Aziz, Sayed Mahfuzul. $3 3615108
856 4 0 $u https://www.sciencedirect.com/science/book/9780128112557