Digital logic design using Verilog =...
Taraate, Vaibbhav.

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  • Digital logic design using Verilog = coding and RTL synthesis /
  • 紀錄類型: 書目-電子資源 : Monograph/item
    正題名/作者: Digital logic design using Verilog/ by Vaibbhav Taraate.
    其他題名: coding and RTL synthesis /
    作者: Taraate, Vaibbhav.
    出版者: Singapore :Springer Singapore : : 2022.,
    面頁冊數: xxv, 604 p. :ill., digital ;24 cm.
    內容註: Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs.
    Contained By: Springer Nature eBook
    標題: Logic design - Data processing. -
    電子資源: https://doi.org/10.1007/978-981-16-3199-3
    ISBN: 9789811631993
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W9437929 電子資源 11.線上閱覽_V 電子書 EB TK7868.L6 T37 2022 一般使用(Normal) 在架 0
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