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Memory Module Design for High-Temper...

Abbasi, Affan.

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Memory Module Design for High-Temperature Applications in SiC CMOS Technology.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Memory Module Design for High-Temperature Applications in SiC CMOS Technology./
作者:	Abbasi, Affan.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2021,
面頁冊數:	131 p.
附註:	Source: Dissertations Abstracts International, Volume: 82-12, Section: B.
Contained By:	Dissertations Abstracts International82-12B.
標題:	Engineering. -
電子資源:	https://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=28492486
ISBN:	9798505511220

Memory Module Design for High-Temperature Applications in SiC CMOS Technology.
Abbasi, Affan.

Memory Module Design for High-Temperature Applications in SiC CMOS Technology. - Ann Arbor : ProQuest Dissertations & Theses, 2021 - 131 p.

Source: Dissertations Abstracts International, Volume: 82-12, Section: B.

Thesis (Ph.D.)--University of Arkansas, 2021.

This item must not be sold to any third party vendors.

The wide bandgap (WBG) characteristics of SiC play a significant and disruptive role in the power electronics industry. The same characteristics make this material a viable choice for high-temperature electronics systems. Leveraging the high-temperature capability of SiC is crucial to automotive, space exploration, aerospace, deep well drilling, and gas turbines. A significant issue with the high-temperature operation is the exponential increase in leakage current. The lower intrinsic carrier concentration of SiC (10-9 cm-3) compared to Si (1010 cm-3) leads to lower leakage over temperature. Several researchers have demonstrated analog and digital circuits designed in SiC. However, a memory module is required to realize a complete electronic system in SiC that bridges the gap between data processing and data storage. Designing memory that can process massive amounts of data in harsh environments while consuming low power opens doors for future electronics. A novel static random-access memory (SRAM) cell is designed and implemented in a SiC 1 µm triple well CMOS process for high-temperature applications in this work. The prevalent issues encountered during SiC fabrication and the uncertainties in device performance led to 6T SRAM cell design modifications that enable adaptability to the worst and the best cases. However, design trade-offs are made in the design size, the number of transistors, number of I/Os, and the cell's power consumption. The novel SRAM cell design mitigates the effect of poor p-type contacts after the device fabrication by controlling the cell's drive strength via an additional pull-up network. The design also includes two parallel access transistors and separate wordlines that control both access transistors. This individual control enables post-fabrication tunability in the cell ratio (CR) and the pull-up (PR) ratio of the cell. It also allows tuning the access transistors' effective width during a data read operation, and a data write operation, independently. Along with the SRAM cell design, the conventional latch-based sense amplifier is also designed in the SiC CMOS process to realize the monolithic memory IC modules. The SRAM cell performance is evaluated on the basis of static noise margin (SNM), write SNM (WSNM), read SNM (RSNM), leakage current, and read access time over a wide temperature range (25 °C to 500 °C) on three uniquely processed wafers. The noise margins measured on Wafer #2 show a lower leakage current of ~500 nA at 500 °C with the supply voltage of 10 V. The SNM of 6.07 V is measured at 500 °C with a 10 V of power supply. The read access time at 400 °C is ~7.5 µs at a supply voltage of 10 V.

ISBN: 9798505511220Subjects--Topical Terms:

586835
Engineering.
Subjects--Index Terms:

CMOS

Memory Module Design for High-Temperature Applications in SiC CMOS Technology.
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520 $a The wide bandgap (WBG) characteristics of SiC play a significant and disruptive role in the power electronics industry. The same characteristics make this material a viable choice for high-temperature electronics systems. Leveraging the high-temperature capability of SiC is crucial to automotive, space exploration, aerospace, deep well drilling, and gas turbines. A significant issue with the high-temperature operation is the exponential increase in leakage current. The lower intrinsic carrier concentration of SiC (10-9 cm-3) compared to Si (1010 cm-3) leads to lower leakage over temperature. Several researchers have demonstrated analog and digital circuits designed in SiC. However, a memory module is required to realize a complete electronic system in SiC that bridges the gap between data processing and data storage. Designing memory that can process massive amounts of data in harsh environments while consuming low power opens doors for future electronics. A novel static random-access memory (SRAM) cell is designed and implemented in a SiC 1 µm triple well CMOS process for high-temperature applications in this work. The prevalent issues encountered during SiC fabrication and the uncertainties in device performance led to 6T SRAM cell design modifications that enable adaptability to the worst and the best cases. However, design trade-offs are made in the design size, the number of transistors, number of I/Os, and the cell's power consumption. The novel SRAM cell design mitigates the effect of poor p-type contacts after the device fabrication by controlling the cell's drive strength via an additional pull-up network. The design also includes two parallel access transistors and separate wordlines that control both access transistors. This individual control enables post-fabrication tunability in the cell ratio (CR) and the pull-up (PR) ratio of the cell. It also allows tuning the access transistors' effective width during a data read operation, and a data write operation, independently. Along with the SRAM cell design, the conventional latch-based sense amplifier is also designed in the SiC CMOS process to realize the monolithic memory IC modules. The SRAM cell performance is evaluated on the basis of static noise margin (SNM), write SNM (WSNM), read SNM (RSNM), leakage current, and read access time over a wide temperature range (25 °C to 500 °C) on three uniquely processed wafers. The noise margins measured on Wafer #2 show a lower leakage current of ~500 nA at 500 °C with the supply voltage of 10 V. The SNM of 6.07 V is measured at 500 °C with a 10 V of power supply. The read access time at 400 °C is ~7.5 µs at a supply voltage of 10 V.
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