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A Time-Mode Neural Network Architecture.

Crowley, Liam.

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A Time-Mode Neural Network Architecture.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	A Time-Mode Neural Network Architecture./
作者:	Crowley, Liam.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2020,
面頁冊數:	96 p.
附註:	Source: Masters Abstracts International, Volume: 82-05.
Contained By:	Masters Abstracts International82-05.
標題:	Electrical engineering. -
電子資源:	https://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=28087975
ISBN:	9798684655050

A Time-Mode Neural Network Architecture.
Crowley, Liam.

A Time-Mode Neural Network Architecture. - Ann Arbor : ProQuest Dissertations & Theses, 2020 - 96 p.

Source: Masters Abstracts International, Volume: 82-05.

Thesis (M.S.)--Tufts University, 2020.

This item must not be sold to any third party vendors.

In this work I present an energy efficient mixed-signal realization of a quantized neural network. In this implementation I represent signals in the time domain. By encoding signals as pulse-widths, we can take advantage of the extremely accurate clocks and delay resolution in nanometer CMOS processes. Weights are represented as binary weighted current sources with local DRAM storage. Capacitive integration implements weighted addition, and an inverter provides as rectified linear activation. I present the design in 0.18um CMOS process with successful circuit and behavioral simulation results on the IRIS dataset.

ISBN: 9798684655050Subjects--Topical Terms:

649834
Electrical engineering.
Subjects--Index Terms:

Analog

A Time-Mode Neural Network Architecture.
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245 1 0 $a A Time-Mode Neural Network Architecture.
260 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2020
300 $a 96 p.
500 $a Source: Masters Abstracts International, Volume: 82-05.
500 $a Advisor: Sonkusale, Sameer.
502 $a Thesis (M.S.)--Tufts University, 2020.
506 $a This item must not be sold to any third party vendors.
520 $a In this work I present an energy efficient mixed-signal realization of a quantized neural network. In this implementation I represent signals in the time domain. By encoding signals as pulse-widths, we can take advantage of the extremely accurate clocks and delay resolution in nanometer CMOS processes. Weights are represented as binary weighted current sources with local DRAM storage. Capacitive integration implements weighted addition, and an inverter provides as rectified linear activation. I present the design in 0.18um CMOS process with successful circuit and behavioral simulation results on the IRIS dataset.
590 $a School code: 0234.
650 4 $a Electrical engineering. $3 649834
650 4 $a Computational physics. $3 3343998
653 $a Analog
653 $a Neural network
653 $a Time
653 $a Time mode
690 $a 0544
690 $a 0216
710 2 $a Tufts University. $b Electrical Engineering. $3 1030762
773 0 $t Masters Abstracts International $g 82-05.
790 $a 0234
791 $a M.S.
792 $a 2020
793 $a English
856 4 0 $u https://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=28087975