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Reconfigurable Convolution Implement...

Bannon, Jesse.

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Reconfigurable Convolution Implementation for CNNs in FPGA.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Reconfigurable Convolution Implementation for CNNs in FPGA./
作者:	Bannon, Jesse.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2018,
面頁冊數:	24 p.
附註:	Source: Masters Abstracts International, Volume: 80-09.
Contained By:	Masters Abstracts International80-09.
標題:	Computer Engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=13423897
ISBN:	9780438872905

Reconfigurable Convolution Implementation for CNNs in FPGA.
Bannon, Jesse.

Reconfigurable Convolution Implementation for CNNs in FPGA. - Ann Arbor : ProQuest Dissertations & Theses, 2018 - 24 p.

Source: Masters Abstracts International, Volume: 80-09.

Thesis (Master's)--University of Washington, 2018.

This item must not be added to any third party search indexes.

Deep learning continues to be the revolutionary method used in pattern recognition applications including image, video, and speech processing. Convolutional Neural Networks (CNNs) in particular have outperformed every competitor in image classification benchmarks, but suffer from high computation and storage complexities. It is becoming more apparent to extend this breakthrough technology to embedded applications that demand low power and mission critical response times. Consequently, embedded CNNs deployed on the edge require compact platforms capable of accelerated computing. Previous works have explored methods to optimize convolution computation within Field Programmable Gate Arrays (FPGAs). Many of which only consider supporting a single CNN architecture. While this approach allows precise optimizations structured around a specific CNN, it restricts the FPGA from updating its model without tremendous compile times upwards to hours. In this work, we explore state-of-the-art CNN-FPGA architectures and implement our own reconfigurable convolution computation unit (CCU) using the Intel High Level Synthesis (HLS) Compiler using a sliding window-based implementation. Results show our CCU does not suffice for real-time computations on the edge.

ISBN: 9780438872905Subjects--Topical Terms:

1567821
Computer Engineering.
Subjects--Index Terms:

CNN

Reconfigurable Convolution Implementation for CNNs in FPGA.
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500 $a Source: Masters Abstracts International, Volume: 80-09.
500 $a Publisher info.: Dissertation/Thesis.
500 $a Advisor: Tolentino, Matthew E.
502 $a Thesis (Master's)--University of Washington, 2018.
506 $a This item must not be added to any third party search indexes.
506 $a This item must not be sold to any third party vendors.
520 $a Deep learning continues to be the revolutionary method used in pattern recognition applications including image, video, and speech processing. Convolutional Neural Networks (CNNs) in particular have outperformed every competitor in image classification benchmarks, but suffer from high computation and storage complexities. It is becoming more apparent to extend this breakthrough technology to embedded applications that demand low power and mission critical response times. Consequently, embedded CNNs deployed on the edge require compact platforms capable of accelerated computing. Previous works have explored methods to optimize convolution computation within Field Programmable Gate Arrays (FPGAs). Many of which only consider supporting a single CNN architecture. While this approach allows precise optimizations structured around a specific CNN, it restricts the FPGA from updating its model without tremendous compile times upwards to hours. In this work, we explore state-of-the-art CNN-FPGA architectures and implement our own reconfigurable convolution computation unit (CCU) using the Intel High Level Synthesis (HLS) Compiler using a sliding window-based implementation. Results show our CCU does not suffice for real-time computations on the edge.
590 $a School code: 0250.
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650 4 $a Computer science. $3 523869
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653 $a Convolution
653 $a FPGA
653 $a HLS
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690 $a 0984
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