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Co-Optimizing Hardware Design and Me...

Ilbeyi, Berkin.

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Co-Optimizing Hardware Design and Meta-Tracing Just-in-Time Compilation.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Co-Optimizing Hardware Design and Meta-Tracing Just-in-Time Compilation./
作者:	Ilbeyi, Berkin.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2019,
面頁冊數:	187 p.
附註:	Source: Dissertations Abstracts International, Volume: 80-12, Section: B.
Contained By:	Dissertations Abstracts International80-12B.
標題:	Computer Engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=13812102
ISBN:	9781392248270

Co-Optimizing Hardware Design and Meta-Tracing Just-in-Time Compilation.
Ilbeyi, Berkin.

Co-Optimizing Hardware Design and Meta-Tracing Just-in-Time Compilation. - Ann Arbor : ProQuest Dissertations & Theses, 2019 - 187 p.

Source: Dissertations Abstracts International, Volume: 80-12, Section: B.

Thesis (Ph.D.)--Cornell University, 2019.

This item must not be sold to any third party vendors.

Performance of computers has enjoyed consistent gains due to the availability of faster and cheaper transistors, more complex hardware designs, and better hardware design tools. Increasing computing performance has also led to the ability to develop more complex software, rising popularity of higher level languages, and better software design tools. Unfortunately, technology scaling is slowing, and hardware and software depend more on each other to continue deliver performance gains in the absence of technology scaling. As single-threaded computing performance slows down, emerging domains such as machine learning are increasingly using custom hardware. The proliferation of domain-specific hardware requires the need for more agile hardware design methodologies. Another trend in the software industry is the rising popularity of dynamic languages. These languages can be slow, but improvements in single-threaded performance and just-in-time (JIT) compilation have improved the performance over the years. As single-threaded performance slows down and software-only JIT techniques provide limited benefits into the future, new approaches are needed to improve the performance of dynamic languages.This thesis aims to address these two related challenges by co-optimizing hardware design and meta-tracing JIT compilation technology. The first thrust of this thesis is to demonstrate meta-tracing JIT virtual machines (VMs) can be instrumental in building agile hardware simulators across different abstraction levels including functional level, cycle level, and register-transfer level (RTL). I first introduce an instruction-set simulator that makes use of meta-tracing JIT compilation to productively define instruction semantics and encodings while rivaling the performance of purpose-built simulators. I then build on this simulator and add JIT-assisted cycle-level modeling and embedding within an existing simulator to achieve a very fast cycle-level simulation methodology. I also demonstrate that a number of simulation-aware JIT and JIT-aware simulation techniques can help productive hardware generation and simulation frameworks to close the performance gap with commercial RTL simulators. The second thrust of this thesis explores hardware acceleration opportunities in meta-tracing JIT VMs and proposes a software/hardware co-optimization scheme that can significantly reduce dynamic instruction count in meta-tracing JIT VMs. For this, I first present a methodology to study and research meta-tracing JIT VMs and perform a detailed cross-layer workload characterization of these VMs. Then I quantify a type of value locality in JIT-compiled code called object dereference locality, and propose a software/hardware co-optimization technique to improve the performance of meta-tracing JIT VMs.

ISBN: 9781392248270Subjects--Topical Terms:

1567821
Computer Engineering.
Subjects--Index Terms:

Compiler

Co-Optimizing Hardware Design and Meta-Tracing Just-in-Time Compilation.
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