東華大學圖書館 |

Language: English

Help

回圖書館首頁

手機版館藏查詢

Back

Switch To: Labeled | MARC Mode | ISBD

Directory Storage Efficiency Improve...

Shu, Wei.

Linked to FindBook

Google Book

Amazon

博客來

Directory Storage Efficiency Improvement for Chip-Multiprocessors.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Directory Storage Efficiency Improvement for Chip-Multiprocessors./
Author:	Shu, Wei.
Published:	Ann Arbor : ProQuest Dissertations & Theses, : 2018,
Description:	120 p.
Notes:	Source: Dissertations Abstracts International, Volume: 80-10, Section: B.
Contained By:	Dissertations Abstracts International80-10B.
Subject:	Computer Engineering. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=13420085
ISBN:	9781392042243

Directory Storage Efficiency Improvement for Chip-Multiprocessors.
Shu, Wei.

Directory Storage Efficiency Improvement for Chip-Multiprocessors. - Ann Arbor : ProQuest Dissertations & Theses, 2018 - 120 p.

Source: Dissertations Abstracts International, Volume: 80-10, Section: B.

Thesis (Ph.D.)--University of Louisiana at Lafayette, 2018.

This item must not be added to any third party search indexes.

Architecting a cache-coherent memory hierarchy for computer processor is challenging for scaled up CMPs. This dissertation investigates two approaches to efficiently support directory based cache-coherent memory for processors. The first approach is dubbed Non-U niform Directory Architec-ture (NUDA) framework aiming at CMP scalability improvement by drastically reducing on-chip directory area overhead. Exploiting our newly observed insights, NUDA employs a multi-level directory conguration in CMP, equipping a small on-chip buer to keep only "active" Directory Vectors (DVs) for sustained execution performance. This dissertation also investigated an efficient on-chip CMP directory design that is featured with relinquishment coherence and compressed sharer tracking (ReCoST) for superior directory storage eciency, aiming to address the shortcomings of excessive directory area overhead. By dropping long runs of zeros in present-bit vectors (PVs) and storing distinct PVs in a sharer pattern table (SPT), directory storage overhead is reduced. In addition, relinquishment coherence is adopted to boost SPT utilization by transforming a PV to its variations, ensuring exact sharer tracking. ReCoST requires no over ow provision, as a result of its unique relinquishment coherence approach.

ISBN: 9781392042243Subjects--Topical Terms:

1567821
Computer Engineering.
Subjects--Index Terms:

Chip-multiprocessors

Directory Storage Efficiency Improvement for Chip-Multiprocessors.
LDR:02551nmm a2200361 4500 001 2269182
005 20200910100152.5
008 220629s2018 ||||||||||||||||| ||eng d
020 $a 9781392042243
035 $a (MiAaPQ)AAI13420085
035 $a (MiAaPQ)louisiana:10971
035 $a AAI13420085
040 $a MiAaPQ $c MiAaPQ
100 1 $a Shu, Wei. $3 3546486
245 1 0 $a Directory Storage Efficiency Improvement for Chip-Multiprocessors.
260 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2018
300 $a 120 p.
500 $a Source: Dissertations Abstracts International, Volume: 80-10, Section: B.
500 $a Publisher info.: Dissertation/Thesis.
500 $a Advisor: Tzeng, Nian-Feng.
502 $a Thesis (Ph.D.)--University of Louisiana at Lafayette, 2018.
506 $a This item must not be added to any third party search indexes.
506 $a This item must not be sold to any third party vendors.
520 $a Architecting a cache-coherent memory hierarchy for computer processor is challenging for scaled up CMPs. This dissertation investigates two approaches to efficiently support directory based cache-coherent memory for processors. The first approach is dubbed Non-U niform Directory Architec-ture (NUDA) framework aiming at CMP scalability improvement by drastically reducing on-chip directory area overhead. Exploiting our newly observed insights, NUDA employs a multi-level directory conguration in CMP, equipping a small on-chip buer to keep only "active" Directory Vectors (DVs) for sustained execution performance. This dissertation also investigated an efficient on-chip CMP directory design that is featured with relinquishment coherence and compressed sharer tracking (ReCoST) for superior directory storage eciency, aiming to address the shortcomings of excessive directory area overhead. By dropping long runs of zeros in present-bit vectors (PVs) and storing distinct PVs in a sharer pattern table (SPT), directory storage overhead is reduced. In addition, relinquishment coherence is adopted to boost SPT utilization by transforming a PV to its variations, ensuring exact sharer tracking. ReCoST requires no over ow provision, as a result of its unique relinquishment coherence approach.
590 $a School code: 1363.
650 4 $a Computer Engineering. $3 1567821
650 4 $a Engineering. $3 586835
653 $a Chip-multiprocessors
653 $a Directory storage efficiency improvement
690 $a 0464
690 $a 0537
710 2 $a University of Louisiana at Lafayette. $b Computer Engineering. $3 3348685
773 0 $t Dissertations Abstracts International $g 80-10B.
790 $a 1363
791 $a Ph.D.
792 $a 2018
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=13420085