東華大學圖書館 |

語系: 繁體中文

說明(常見問題)

回圖書館首頁

手機版館藏查詢

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

High-Speed Low-Power Analog to Digit...

Nazari, Ali.

FindBook

Google Book

Amazon

博客來

High-Speed Low-Power Analog to Digital Converter for Digital Beam Forming Systems.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	High-Speed Low-Power Analog to Digital Converter for Digital Beam Forming Systems./
作者:	Nazari, Ali.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, : 2017,
面頁冊數:	88 p.
附註:	Source: Dissertations Abstracts International, Volume: 78-11, Section: B.
Contained By:	Dissertations Abstracts International78-11B.
標題:	Electrical engineering. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10276247
ISBN:	9781369768718

High-Speed Low-Power Analog to Digital Converter for Digital Beam Forming Systems.
Nazari, Ali.

High-Speed Low-Power Analog to Digital Converter for Digital Beam Forming Systems. - Ann Arbor : ProQuest Dissertations & Theses, 2017 - 88 p.

Source: Dissertations Abstracts International, Volume: 78-11, Section: B.

Thesis (Ph.D.)--Arizona State University, 2017.

This item must not be sold to any third party vendors.

Time-interleaved analog to digital converters (ADCs) have become critical components in high-speed communication systems. Consumers demands for smaller size, more bandwidth and more features from their communication systems have driven the market to use modern complementary metal-oxide-semiconductor (CMOS) technologies with shorter channel-length transistors and hence a more compact design. Downscaling the supply voltage which is required in submicron technologies benefits digital circuits in terms of power and area. Designing accurate analog circuits, however becomes more challenging due to the less headroom. One way to overcome this problem is to use calibration to compensate for the loss of accuracy in analog circuits. Time-interleaving increases the effective data conversion rate in ADCs while keeping the circuit requirements the same. However, this technique needs special considerations as other design issues associated with using parallel identical channels emerge. The first and the most important is the practical issue of timing mismatch between channels, also called sample-time error, which can directly affect the performance of the ADC. Many techniques have been developed to tackle this issue both in analog and digital domains. Most of these techniques have high complexities especially when the number of channels exceeds 2 and some of them are only valid when input signal is a single tone sinusoidal which limits the application. This dissertation proposes a sample-time error calibration technique which bests the previous techniques in terms of simplicity, and also could be used with arbitrary input signals. A 12-bit 650 MSPS pipeline ADC with 1.5 GHz analog bandwidth for digital beam forming systems is designed in IBM 8HP BiCMOS 130 nm technology. A front-end sample-and-hold amplifier (SHA) was also designed to compare with an SHA-less design in terms of performance, power and area. Simulation results show that the proposed technique is able to improve the SNDR by 20 dB for a mismatch of 50% of the sampling period and up to 29 dB at 37% of the Nyquist frequency. The designed ADC consumes 122 mW in each channel and the clock generation circuit consumes 142 mW. The ADC achieves 68.4 dB SNDR for an input of 61 MHz.

ISBN: 9781369768718Subjects--Topical Terms:

649834
Electrical engineering.
Subjects--Index Terms:

Analog to digital converters

High-Speed Low-Power Analog to Digital Converter for Digital Beam Forming Systems.
LDR:03487nmm a2200361 4500 001 2267244
005 20200623064714.5
008 220629s2017 ||||||||||||||||| ||eng d
020 $a 9781369768718
035 $a (MiAaPQ)AAI10276247
035 $a (MiAaPQ)asu:17086
035 $a AAI10276247
040 $a MiAaPQ $c MiAaPQ
100 1 $a Nazari, Ali. $3 3509981
245 1 0 $a High-Speed Low-Power Analog to Digital Converter for Digital Beam Forming Systems.
260 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2017
300 $a 88 p.
500 $a Source: Dissertations Abstracts International, Volume: 78-11, Section: B.
500 $a Publisher info.: Dissertation/Thesis.
500 $a Advisor: Barnaby, Hugh James.
502 $a Thesis (Ph.D.)--Arizona State University, 2017.
506 $a This item must not be sold to any third party vendors.
520 $a Time-interleaved analog to digital converters (ADCs) have become critical components in high-speed communication systems. Consumers demands for smaller size, more bandwidth and more features from their communication systems have driven the market to use modern complementary metal-oxide-semiconductor (CMOS) technologies with shorter channel-length transistors and hence a more compact design. Downscaling the supply voltage which is required in submicron technologies benefits digital circuits in terms of power and area. Designing accurate analog circuits, however becomes more challenging due to the less headroom. One way to overcome this problem is to use calibration to compensate for the loss of accuracy in analog circuits. Time-interleaving increases the effective data conversion rate in ADCs while keeping the circuit requirements the same. However, this technique needs special considerations as other design issues associated with using parallel identical channels emerge. The first and the most important is the practical issue of timing mismatch between channels, also called sample-time error, which can directly affect the performance of the ADC. Many techniques have been developed to tackle this issue both in analog and digital domains. Most of these techniques have high complexities especially when the number of channels exceeds 2 and some of them are only valid when input signal is a single tone sinusoidal which limits the application. This dissertation proposes a sample-time error calibration technique which bests the previous techniques in terms of simplicity, and also could be used with arbitrary input signals. A 12-bit 650 MSPS pipeline ADC with 1.5 GHz analog bandwidth for digital beam forming systems is designed in IBM 8HP BiCMOS 130 nm technology. A front-end sample-and-hold amplifier (SHA) was also designed to compare with an SHA-less design in terms of performance, power and area. Simulation results show that the proposed technique is able to improve the SNDR by 20 dB for a mismatch of 50% of the sampling period and up to 29 dB at 37% of the Nyquist frequency. The designed ADC consumes 122 mW in each channel and the clock generation circuit consumes 142 mW. The ADC achieves 68.4 dB SNDR for an input of 61 MHz.
590 $a School code: 0010.
650 4 $a Electrical engineering. $3 649834
653 $a Analog to digital converters
653 $a Integrated circuit design
653 $a Mixed-signal calibration
653 $a Time-interleaved adcs
690 $a 0544
710 2 $a Arizona State University. $b Electrical Engineering. $3 1671741
773 0 $t Dissertations Abstracts International $g 78-11B.
790 $a 0010
791 $a Ph.D.
792 $a 2017
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10276247