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Convolutional Neural Network Acceler...

Yendapally, Harshitha.

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Convolutional Neural Network Accelerator Based on Pynq Fp.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Convolutional Neural Network Accelerator Based on Pynq Fp./
Author:	Yendapally, Harshitha.
Published:	Ann Arbor : ProQuest Dissertations & Theses, : 2019,
Description:	82 p.
Notes:	Source: Masters Abstracts International, Volume: 80-12.
Contained By:	Masters Abstracts International80-12.
Subject:	Computer Engineering. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=13877952
ISBN:	9781392180921

Convolutional Neural Network Accelerator Based on Pynq Fp.
Yendapally, Harshitha.

Convolutional Neural Network Accelerator Based on Pynq Fp. - Ann Arbor : ProQuest Dissertations & Theses, 2019 - 82 p.

Source: Masters Abstracts International, Volume: 80-12.

Thesis (M.S.)--The University of Texas at San Antonio, 2019.

This item must not be sold to any third party vendors.

In deep learning applications, speed and performance are of utmost importance, which is often provided by neural network accelerators. The neural network accelerator is a hardware design used in artificial intelligent (AI) applications to improve efficiency. The Convolutional Neural Networks (CNNs) are used in training and testing of AI applications. The design complexity of CNNs has been steadily increasing to improve accuracy. To achieve high accuracy, CNNs need massive amount of computations and bulk resources. To support high speed functionality and efficient resource management, customized hardware accelerator units targeting AI applications can be designed leveraging computer architecture concepts such as architecture pipelining.The objective of this research is the design and development of an optimized Field Programmable Gate Arrays (FPGA) based accelerator for convolutional neural networks (CNNs). The neural network accelerator is implemented by the concept of embedding customized hardware multiplier with Xilinx FPGA board files. To improve the performance of the designed hardware, architecture concepts are utilized to reduce the access time required for the neural network application. The dependency of the neural network accelerator performance on utilization of hardware resources is analyzed in detail in this thesis. A comparative analysis of the different optimization techniques based on performance and resource utilization is also carried out. A comparative performance analysis of the fixed-point numerical representation with floating-point numerical representation on the neural network accelerator is also presented. These analyses are carried out taking accuracy into consideration.

ISBN: 9781392180921Subjects--Topical Terms:

1567821
Computer Engineering.

Convolutional Neural Network Accelerator Based on Pynq Fp.
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100 1 $a Yendapally, Harshitha. $3 3541366
245 1 0 $a Convolutional Neural Network Accelerator Based on Pynq Fp.
260 1 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2019
300 $a 82 p.
500 $a Source: Masters Abstracts International, Volume: 80-12.
500 $a Publisher info.: Dissertation/Thesis.
500 $a Advisor: John, Eugene B.
502 $a Thesis (M.S.)--The University of Texas at San Antonio, 2019.
506 $a This item must not be sold to any third party vendors.
520 $a In deep learning applications, speed and performance are of utmost importance, which is often provided by neural network accelerators. The neural network accelerator is a hardware design used in artificial intelligent (AI) applications to improve efficiency. The Convolutional Neural Networks (CNNs) are used in training and testing of AI applications. The design complexity of CNNs has been steadily increasing to improve accuracy. To achieve high accuracy, CNNs need massive amount of computations and bulk resources. To support high speed functionality and efficient resource management, customized hardware accelerator units targeting AI applications can be designed leveraging computer architecture concepts such as architecture pipelining.The objective of this research is the design and development of an optimized Field Programmable Gate Arrays (FPGA) based accelerator for convolutional neural networks (CNNs). The neural network accelerator is implemented by the concept of embedding customized hardware multiplier with Xilinx FPGA board files. To improve the performance of the designed hardware, architecture concepts are utilized to reduce the access time required for the neural network application. The dependency of the neural network accelerator performance on utilization of hardware resources is analyzed in detail in this thesis. A comparative analysis of the different optimization techniques based on performance and resource utilization is also carried out. A comparative performance analysis of the fixed-point numerical representation with floating-point numerical representation on the neural network accelerator is also presented. These analyses are carried out taking accuracy into consideration.
590 $a School code: 1283.
650 4 $a Computer Engineering. $3 1567821
690 $a 0464
710 2 $a The University of Texas at San Antonio. $b Electrical and Computer Engineering. $3 2104320
773 0 $t Masters Abstracts International $g 80-12.
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791 $a M.S.
792 $a 2019
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=13877952