東華大學圖書館 |

Language: English

Help

回圖書館首頁

手機版館藏查詢

Back

Switch To: Labeled | MARC Mode | ISBD

Mitigating process variability and s...

Zimpeck, Alexandra.

Linked to FindBook

Google Book

Amazon

博客來

Mitigating process variability and soft errors at circuit-level for FinFETs

Record Type:	Electronic resources : Monograph/item
Title/Author:	Mitigating process variability and soft errors at circuit-level for FinFETs/ by Alexandra Zimpeck ... [et al.].
other author:	Zimpeck, Alexandra.
Published:	Cham :Springer International Publishing : : 2021.,
Description:	xiii, 131 p. :ill., digital ;24 cm.
[NT 15003449]:	Chapter 1. Introduction -- Chapter 2. FinFET Technology -- Chapter 3. Reliability Challenges in FinFETs -- Chapter 4. Circuit-Level Mitigation Approaches -- Chapter 5. Evaluation Methodology -- Chapter 6. Process Variability Mitigation -- Chapter 7. Soft Error Mitigation -- Chapter 8. General Trade-offs -- Chapter 9. Final Remarks.
Contained By:	Springer Nature eBook
Subject:	Field-effect transistors - Design and construction. -
Online resource:	https://doi.org/10.1007/978-3-030-68368-9
ISBN:	9783030683689

Mitigating process variability and soft errors at circuit-level for FinFETs
Mitigating process variability and soft errors at circuit-level for FinFETs[electronic resource] /by Alexandra Zimpeck ... [et al.]. - Cham :Springer International Publishing :2021. - xiii, 131 p. :ill., digital ;24 cm.

Chapter 1. Introduction -- Chapter 2. FinFET Technology -- Chapter 3. Reliability Challenges in FinFETs -- Chapter 4. Circuit-Level Mitigation Approaches -- Chapter 5. Evaluation Methodology -- Chapter 6. Process Variability Mitigation -- Chapter 7. Soft Error Mitigation -- Chapter 8. General Trade-offs -- Chapter 9. Final Remarks.

This book evaluates the influence of process variations (e.g. work-function fluctuations) and radiation-induced soft errors in a set of logic cells using FinFET technology, considering the 7nm technological node as a case study. Moreover, for accurate soft error estimation, the authors adopt a radiation event generator tool (MUSCA SEP3), which deals both with layout features and electrical properties of devices. The authors also explore four circuit-level techniques (e.g. transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor) as alternatives to attenuate the unwanted effects on FinFET logic cells. This book also evaluates the mitigation tendency when different levels of process variation, transistor sizing, and radiation particle characteristics are applied in the design. An overall comparison of all methods addressed by this work is provided allowing to trace a trade-off between the reliability gains and the design penalties of each approach regarding the area, performance, power consumption, single event transient (SET) pulse width, and SET cross-section. Explains how to measure the influence of process variability (e.g. work-function fluctuations) and radiation-induced soft errors in FinFET logic cells; Enables designers to improve the robustness of FinFET integrated circuits without focusing on manufacturing adjustments; Discusses the benefits and downsides of using circuit-level approaches such as transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor for mitigating the impact of process variability and soft errors; Evaluates the techniques described in the context of different test scenarios: distinct levels of process variations, transistor sizing, and different radiation features; Helps readers identify the best circuit design considering the target application and design requirements like area constraints or power/delay limitations.

ISBN: 9783030683689

Standard No.: 10.1007/978-3-030-68368-9doiSubjects--Topical Terms:

3492710
Field-effect transistors
--Design and construction.

LC Class. No.: TK7871.95

Dewey Class. No.: 621.3815284

Mitigating process variability and soft errors at circuit-level for FinFETs
LDR:03261nmm a2200325 a 4500 001 2239067
003 DE-He213
005 20210706103350.0
006 m d
007 cr nn 008maaau
008 211111s2021 sz s 0 eng d
020 $a 9783030683689 $q (electronic bk.)
020 $a 9783030683672 $q (paper)
024 7 $a 10.1007/978-3-030-68368-9 $2 doi
035 $a 978-3-030-68368-9
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7871.95
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815284 $2 23
090 $a TK7871.95 $b .M684 2021
245 0 0 $a Mitigating process variability and soft errors at circuit-level for FinFETs $h [electronic resource] / $c by Alexandra Zimpeck ... [et al.].
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2021.
300 $a xiii, 131 p. : $b ill., digital ; $c 24 cm.
505 0 $a Chapter 1. Introduction -- Chapter 2. FinFET Technology -- Chapter 3. Reliability Challenges in FinFETs -- Chapter 4. Circuit-Level Mitigation Approaches -- Chapter 5. Evaluation Methodology -- Chapter 6. Process Variability Mitigation -- Chapter 7. Soft Error Mitigation -- Chapter 8. General Trade-offs -- Chapter 9. Final Remarks.
520 $a This book evaluates the influence of process variations (e.g. work-function fluctuations) and radiation-induced soft errors in a set of logic cells using FinFET technology, considering the 7nm technological node as a case study. Moreover, for accurate soft error estimation, the authors adopt a radiation event generator tool (MUSCA SEP3), which deals both with layout features and electrical properties of devices. The authors also explore four circuit-level techniques (e.g. transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor) as alternatives to attenuate the unwanted effects on FinFET logic cells. This book also evaluates the mitigation tendency when different levels of process variation, transistor sizing, and radiation particle characteristics are applied in the design. An overall comparison of all methods addressed by this work is provided allowing to trace a trade-off between the reliability gains and the design penalties of each approach regarding the area, performance, power consumption, single event transient (SET) pulse width, and SET cross-section. Explains how to measure the influence of process variability (e.g. work-function fluctuations) and radiation-induced soft errors in FinFET logic cells; Enables designers to improve the robustness of FinFET integrated circuits without focusing on manufacturing adjustments; Discusses the benefits and downsides of using circuit-level approaches such as transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor for mitigating the impact of process variability and soft errors; Evaluates the techniques described in the context of different test scenarios: distinct levels of process variations, transistor sizing, and different radiation features; Helps readers identify the best circuit design considering the target application and design requirements like area constraints or power/delay limitations.
650 0 $a Field-effect transistors $x Design and construction. $3 3492710
650 0 $a Field-effect transistors $x Reliability. $3 3492711
650 0 $a Soft errors (Computer science) $3 2182962
650 1 4 $a Circuits and Systems. $3 896527
650 2 4 $a Electronic Circuits and Devices. $3 1245773
700 1 $a Zimpeck, Alexandra. $3 3492709
710 2 $a SpringerLink (Online service) $3 836513
773 0 $t Springer Nature eBook
856 4 0 $u https://doi.org/10.1007/978-3-030-68368-9
950 $a Engineering (SpringerNature-11647)