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ASIC design and synthesis = RTL desi...

Taraate, Vaibbhav.

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ASIC design and synthesis = RTL design using Verilog /

Record Type:	Electronic resources : Monograph/item
Title/Author:	ASIC design and synthesis/ by Vaibbhav Taraate.
Reminder of title:	RTL design using Verilog /
Author:	Taraate, Vaibbhav.
Published:	Singapore :Springer Singapore : : 2021.,
Description:	xxi, 330 p. :ill., digital ;24 cm.
[NT 15003449]:	Chapter 1. Introduction -- Chapter 2. Design using CMOS -- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL) -- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL) -- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL) -- Chapter 6. ASIC design guidelines -- Chapter 7. ASIC RTL Verification -- Chapter 8. FSM using VHDL and synthesis -- Chapter 9. ASIC design improvement techniques -- Chapter 10. ASIC Synthesis using Synopsys DC -- Chapter 11. Design for Testability -- Chapter 12. Static timing analysis -- Chapter 13. Multiple Clock domain designs -- Chapter 14. Low power ASIC design -- Chapter 15. ASIC Physical design.
Contained By:	Springer Nature eBook
Subject:	Application-specific integrated circuits - Design. -
Online resource:	https://doi.org/10.1007/978-981-33-4642-0
ISBN:	9789813346420

ASIC design and synthesis = RTL design using Verilog /
Taraate, Vaibbhav.

ASIC design and synthesisRTL design using Verilog /[electronic resource] :by Vaibbhav Taraate. - Singapore :Springer Singapore :2021. - xxi, 330 p. :ill., digital ;24 cm.

Chapter 1. Introduction -- Chapter 2. Design using CMOS -- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL) -- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL) -- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL) -- Chapter 6. ASIC design guidelines -- Chapter 7. ASIC RTL Verification -- Chapter 8. FSM using VHDL and synthesis -- Chapter 9. ASIC design improvement techniques -- Chapter 10. ASIC Synthesis using Synopsys DC -- Chapter 11. Design for Testability -- Chapter 12. Static timing analysis -- Chapter 13. Multiple Clock domain designs -- Chapter 14. Low power ASIC design -- Chapter 15. ASIC Physical design.

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

ISBN: 9789813346420

Standard No.: 10.1007/978-981-33-4642-0doiSubjects--Topical Terms:

3220634
Application-specific integrated circuits
--Design.

LC Class. No.: TK7874.6 / .T373 2021

Dewey Class. No.: 621.3815

ASIC design and synthesis = RTL design using Verilog /
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300 $a xxi, 330 p. : $b ill., digital ; $c 24 cm.
505 0 $a Chapter 1. Introduction -- Chapter 2. Design using CMOS -- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL) -- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL) -- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL) -- Chapter 6. ASIC design guidelines -- Chapter 7. ASIC RTL Verification -- Chapter 8. FSM using VHDL and synthesis -- Chapter 9. ASIC design improvement techniques -- Chapter 10. ASIC Synthesis using Synopsys DC -- Chapter 11. Design for Testability -- Chapter 12. Static timing analysis -- Chapter 13. Multiple Clock domain designs -- Chapter 14. Low power ASIC design -- Chapter 15. ASIC Physical design.
520 $a This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.
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650 2 4 $a Logic Design. $3 892735
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