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Hardware architectures for post-quan...

Soni, Deepraj.

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Hardware architectures for post-quantum digital signature schemes

Record Type:	Electronic resources : Monograph/item
Title/Author:	Hardware architectures for post-quantum digital signature schemes/ by Deepraj Soni ... [et al.].
other author:	Soni, Deepraj.
Published:	Cham :Springer International Publishing : : 2021.,
Description:	xxii, 170 p. :ill., digital ;24 cm.
[NT 15003449]:	Introduction -- qTESLA -- CRYSTALS -Dilithium -- MQDSS -- SPHINCS -- Luov -- Falcon -- Picnic -- GeMSS -- Power, Performance, Area, and Security (PPAS) Comparison of the PQC Algorithms -- Conclusions.
Contained By:	Springer Nature eBook
Subject:	Cryptography. -
Online resource:	https://doi.org/10.1007/978-3-030-57682-0
ISBN:	9783030576820

Hardware architectures for post-quantum digital signature schemes
Hardware architectures for post-quantum digital signature schemes[electronic resource] /by Deepraj Soni ... [et al.]. - Cham :Springer International Publishing :2021. - xxii, 170 p. :ill., digital ;24 cm.

Introduction -- qTESLA -- CRYSTALS -Dilithium -- MQDSS -- SPHINCS -- Luov -- Falcon -- Picnic -- GeMSS -- Power, Performance, Area, and Security (PPAS) Comparison of the PQC Algorithms -- Conclusions.

This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs. Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based; Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms; Enables designers to build hardware implementations that are resilient to a variety of side-channels.

ISBN: 9783030576820

Standard No.: 10.1007/978-3-030-57682-0doiSubjects--Topical Terms:

532586
Cryptography.

LC Class. No.: TK5102.94

Dewey Class. No.: 005.824

Hardware architectures for post-quantum digital signature schemes
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245 0 0 $a Hardware architectures for post-quantum digital signature schemes $h [electronic resource] / $c by Deepraj Soni ... [et al.].
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505 0 $a Introduction -- qTESLA -- CRYSTALS -Dilithium -- MQDSS -- SPHINCS -- Luov -- Falcon -- Picnic -- GeMSS -- Power, Performance, Area, and Security (PPAS) Comparison of the PQC Algorithms -- Conclusions.
520 $a This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs. Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based; Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms; Enables designers to build hardware implementations that are resilient to a variety of side-channels.
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650 0 $a Computer algorithms. $3 523872
650 0 $a Quantum computing. $3 2115803
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650 2 4 $a Processor Architectures. $3 892680
700 1 $a Soni, Deepraj. $3 3486939
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