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SystemVerilog for hardware descripti...

Taraate, Vaibbhav.

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SystemVerilog for hardware description = RTL design and verification /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	SystemVerilog for hardware description/ by Vaibbhav Taraate.
其他題名:	RTL design and verification /
作者:	Taraate, Vaibbhav.
出版者:	Singapore :Springer Singapore : : 2020.,
面頁冊數:	xxi, 252 p. :ill., digital ;24 cm.
內容註:	Chapter 1: Introduction to FPGA design -- Chapter 2: Introduction to HDL -- Chapter 3:Introduction to SystemVerilog -- Chapter 4: Programming using SystemVerilog -- Chapter 5:Combinational design using SystemVerilog -- Chapter 6: Sequential design using SystemVerilog -- Chapter 7: RTL design using SystemVerilog -- Chapter 8: Verification using SystemVerilog -- Chapter 9: Design Implementation using FPGA.
Contained By:	Springer eBooks
標題:	SystemVerilog (Computer hardware description language) -
電子資源:	https://doi.org/10.1007/978-981-15-4405-7
ISBN:	9789811544057

SystemVerilog for hardware description = RTL design and verification /
Taraate, Vaibbhav.

SystemVerilog for hardware descriptionRTL design and verification /[electronic resource] :by Vaibbhav Taraate. - Singapore :Springer Singapore :2020. - xxi, 252 p. :ill., digital ;24 cm.

Chapter 1: Introduction to FPGA design -- Chapter 2: Introduction to HDL -- Chapter 3:Introduction to SystemVerilog -- Chapter 4: Programming using SystemVerilog -- Chapter 5:Combinational design using SystemVerilog -- Chapter 6: Sequential design using SystemVerilog -- Chapter 7: RTL design using SystemVerilog -- Chapter 8: Verification using SystemVerilog -- Chapter 9: Design Implementation using FPGA.

This book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC.

ISBN: 9789811544057

Standard No.: 10.1007/978-981-15-4405-7doiSubjects--Topical Terms:

2132678
SystemVerilog (Computer hardware description language)

LC Class. No.: TK7885.7 / .T373 2020

Dewey Class. No.: 621.392

SystemVerilog for hardware description = RTL design and verification /
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505 0 $a Chapter 1: Introduction to FPGA design -- Chapter 2: Introduction to HDL -- Chapter 3:Introduction to SystemVerilog -- Chapter 4: Programming using SystemVerilog -- Chapter 5:Combinational design using SystemVerilog -- Chapter 6: Sequential design using SystemVerilog -- Chapter 7: RTL design using SystemVerilog -- Chapter 8: Verification using SystemVerilog -- Chapter 9: Design Implementation using FPGA.
520 $a This book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC.
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