語系:
繁體中文
English
說明(常見問題)
回圖書館首頁
手機版館藏查詢
登入
回首頁
切換:
標籤
|
MARC模式
|
ISBD
System Verilog assertions and functi...
~
Mehta, Ashok B.
FindBook
Google Book
Amazon
博客來
System Verilog assertions and functional coverage = guide to language, methodology and applications /
紀錄類型:
書目-電子資源 : Monograph/item
正題名/作者:
System Verilog assertions and functional coverage/ by Ashok B. Mehta.
其他題名:
guide to language, methodology and applications /
作者:
Mehta, Ashok B.
出版者:
Cham :Springer International Publishing : : 2020.,
面頁冊數:
xxxix, 507 p. :ill. (some col.), digital ;24 cm.
內容註:
Introduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions - Basics (sequence, property, assert) -- Sampled Value Functions $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- 'expect' -- 'assume' and formal (static functional) verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-1800-2009 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions - LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options.
Contained By:
Springer eBooks
標題:
Verilog (Computer hardware description language) -
電子資源:
https://doi.org/10.1007/978-3-030-24737-9
ISBN:
9783030247379
System Verilog assertions and functional coverage = guide to language, methodology and applications /
Mehta, Ashok B.
System Verilog assertions and functional coverage
guide to language, methodology and applications /[electronic resource] :by Ashok B. Mehta. - Third edition. - Cham :Springer International Publishing :2020. - xxxix, 507 p. :ill. (some col.), digital ;24 cm.
Introduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions - Basics (sequence, property, assert) -- Sampled Value Functions $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- 'expect' -- 'assume' and formal (static functional) verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-1800-2009 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions - LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options.
ISBN: 9783030247379
Standard No.: 10.1007/978-3-030-24737-9doiSubjects--Topical Terms:
709274
Verilog (Computer hardware description language)
LC Class. No.: TK7885.7 / .M44 2020
Dewey Class. No.: 621.392
System Verilog assertions and functional coverage = guide to language, methodology and applications /
LDR
:01676nmm a2200325 a 4500
001
2214212
003
DE-He213
005
20200302155232.0
006
m d
007
cr nn 008maaau
008
201118s2020 sz s 0 eng d
020
$a
9783030247379
$q
(electronic bk.)
020
$a
9783030247362
$q
(paper)
024
7
$a
10.1007/978-3-030-24737-9
$2
doi
035
$a
978-3-030-24737-9
040
$a
GP
$c
GP
041
0
$a
eng
050
4
$a
TK7885.7
$b
.M44 2020
072
7
$a
TJFC
$2
bicssc
072
7
$a
TEC008010
$2
bisacsh
072
7
$a
TJFC
$2
thema
082
0 4
$a
621.392
$2
23
090
$a
TK7885.7
$b
.M498 2020
100
1
$a
Mehta, Ashok B.
$3
2054674
245
1 0
$a
System Verilog assertions and functional coverage
$h
[electronic resource] :
$b
guide to language, methodology and applications /
$c
by Ashok B. Mehta.
250
$a
Third edition.
260
$a
Cham :
$b
Springer International Publishing :
$b
Imprint: Springer,
$c
2020.
300
$a
xxxix, 507 p. :
$b
ill. (some col.), digital ;
$c
24 cm.
505
0
$a
Introduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions - Basics (sequence, property, assert) -- Sampled Value Functions $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- 'expect' -- 'assume' and formal (static functional) verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-1800-2009 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions - LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options.
650
0
$a
Verilog (Computer hardware description language)
$3
709274
650
0
$a
Electronic digital computers
$x
Design and construction.
$3
552726
650
0
$a
Integrated circuits
$x
Verification.
$3
827163
650
1 4
$a
Circuits and Systems.
$3
896527
650
2 4
$a
Electronics and Microelectronics, Instrumentation.
$3
893838
650
2 4
$a
Processor Architectures.
$3
892680
710
2
$a
SpringerLink (Online service)
$3
836513
773
0
$t
Springer eBooks
856
4 0
$u
https://doi.org/10.1007/978-3-030-24737-9
950
$a
Engineering (Springer-11647)
筆 0 讀者評論
館藏地:
全部
電子資源
出版年:
卷號:
館藏
1 筆 • 頁數 1 •
1
條碼號
典藏地名稱
館藏流通類別
資料類型
索書號
使用類型
借閱狀態
預約狀態
備註欄
附件
W9389125
電子資源
11.線上閱覽_V
電子書
EB TK7885.7 .M44 2020
一般使用(Normal)
在架
0
1 筆 • 頁數 1 •
1
多媒體
評論
新增評論
分享你的心得
Export
取書館
處理中
...
變更密碼
登入