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Design and testing of reversible logic

Singh, Ashutosh Kumar.

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Design and testing of reversible logic

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Design and testing of reversible logic/ edited by Ashutosh Kumar Singh, Masahiro Fujita, Anand Mohan.
其他作者:	Singh, Ashutosh Kumar.
出版者:	Singapore :Springer Singapore : : 2020.,
面頁冊數:	xiv, 265 p. :ill. (some col.), digital ;24 cm.
內容註:	Preface -- Introduction -- Fundamental Concepts -- Design Approaches -- Test Approaches -- Fault Tolerance in Reversible Circuits -- Applications to Emerging Technologies -- Physical Implementation Techniques.
Contained By:	Springer eBooks
標題:	Logic circuits - Design and construction. -
電子資源:	https://doi.org/10.1007/978-981-13-8821-7
ISBN:	9789811388217

Design and testing of reversible logic
Design and testing of reversible logic[electronic resource] /edited by Ashutosh Kumar Singh, Masahiro Fujita, Anand Mohan. - Singapore :Springer Singapore :2020. - xiv, 265 p. :ill. (some col.), digital ;24 cm. - Lecture notes in electrical engineering,v.5771876-1100 ;. - Lecture notes in electrical engineering ;v.577..

Preface -- Introduction -- Fundamental Concepts -- Design Approaches -- Test Approaches -- Fault Tolerance in Reversible Circuits -- Applications to Emerging Technologies -- Physical Implementation Techniques.

The book compiles efficient design and test methodologies for the implementation of reversible logic circuits. The methodologies covered in the book are design approaches, test approaches, fault tolerance in reversible circuits and physical implementation techniques. The book also covers the challenges and the reversible logic circuits to meet these challenges stimulated during each stage of work cycle. The novel computing paradigms are being explored to serve as a basis for fast and low power computation.

ISBN: 9789811388217

Standard No.: 10.1007/978-981-13-8821-7doiSubjects--Topical Terms:

842969
Logic circuits
--Design and construction.

LC Class. No.: TK7868.L6 / D47 2020

Dewey Class. No.: 621.395

Design and testing of reversible logic
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