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Integration of Rijndael-256 Bits Blo...

Cintas Canto, Alvaro.

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Integration of Rijndael-256 Bits Block Size with 256 Bits Key-In A FPGA with SDRAM To Perform Real-Time Video Encryption.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Integration of Rijndael-256 Bits Block Size with 256 Bits Key-In A FPGA with SDRAM To Perform Real-Time Video Encryption./
Author:	Cintas Canto, Alvaro.
Published:	Ann Arbor : ProQuest Dissertations & Theses, : 2018,
Description:	85 p.
Notes:	Source: Masters Abstracts International, Volume: 79-11.
Contained By:	Masters Abstracts International79-11.
Subject:	Computer Engineering. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10791291
ISBN:	9780355940688

Integration of Rijndael-256 Bits Block Size with 256 Bits Key-In A FPGA with SDRAM To Perform Real-Time Video Encryption.
Cintas Canto, Alvaro.

Integration of Rijndael-256 Bits Block Size with 256 Bits Key-In A FPGA with SDRAM To Perform Real-Time Video Encryption. - Ann Arbor : ProQuest Dissertations & Theses, 2018 - 85 p.

Source: Masters Abstracts International, Volume: 79-11.

Thesis (M.S.)--Tennessee Technological University, 2018.

This item must not be sold to any third party vendors.

The increase of real-time video applications has led to the increase of interest in securing them. Security of real-time video capture and streaming is the main motivation behind this research area. Video encryption is one of the ways to protect real-time video data, but it is challenging since the real time video has to meet stringent timing constraints. This thesis introduces an extended version of the Advanced Encryption Standard (AES) with block size and key size of 256-bits long each, also called Rijndael-256-256, to produce a successful lightweight video encryption. This algorithm is designed to provide a very high level of security and yield real-time video needs for reconfigurable logic devices. This new design uses a fully-pipelined AES architecture and follows the protocols of the Rijndael mathematical algorithm, which creates a successful and extended encryption method. The synchronous dynamic random-access memory (SDRAM) provides the input plaintexts, and after they are read and encrypted, the ciphertexts are written back into the SDRAM. The process is periodic, and the period is measured through simulation to test for real-time video encryption. A hardware implementation of this system is verified using a field-programmable gate array (FPGA) and Quartus II package via Signal-Tap. This verification shows the efficiency of the Rijndael-256-256 in reconfigurable logic devices. The proposed encryption method provides a throughput of 57.7x106 b/s, providing real-time video encryption at video frame rate of 188 frame/s, with a frame size of 120 x 160 pixels, or 15 frames/s with a frame size of 480x480 pixels.

ISBN: 9780355940688Subjects--Topical Terms:

1567821
Computer Engineering.

Integration of Rijndael-256 Bits Block Size with 256 Bits Key-In A FPGA with SDRAM To Perform Real-Time Video Encryption.
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506 $a This item must not be sold to any third party vendors.
520 $a The increase of real-time video applications has led to the increase of interest in securing them. Security of real-time video capture and streaming is the main motivation behind this research area. Video encryption is one of the ways to protect real-time video data, but it is challenging since the real time video has to meet stringent timing constraints. This thesis introduces an extended version of the Advanced Encryption Standard (AES) with block size and key size of 256-bits long each, also called Rijndael-256-256, to produce a successful lightweight video encryption. This algorithm is designed to provide a very high level of security and yield real-time video needs for reconfigurable logic devices. This new design uses a fully-pipelined AES architecture and follows the protocols of the Rijndael mathematical algorithm, which creates a successful and extended encryption method. The synchronous dynamic random-access memory (SDRAM) provides the input plaintexts, and after they are read and encrypted, the ciphertexts are written back into the SDRAM. The process is periodic, and the period is measured through simulation to test for real-time video encryption. A hardware implementation of this system is verified using a field-programmable gate array (FPGA) and Quartus II package via Signal-Tap. This verification shows the efficiency of the Rijndael-256-256 in reconfigurable logic devices. The proposed encryption method provides a throughput of 57.7x106 b/s, providing real-time video encryption at video frame rate of 188 frame/s, with a frame size of 120 x 160 pixels, or 15 frames/s with a frame size of 480x480 pixels.
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