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Architectural Techniques for Disturb...

SeyedzadehDelcheh, SeyedMohammad.

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Architectural Techniques for Disturbance Mitigation in Future Memory Systems.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Architectural Techniques for Disturbance Mitigation in Future Memory Systems./
Author:	SeyedzadehDelcheh, SeyedMohammad.
Published:	Ann Arbor : ProQuest Dissertations & Theses, : 2018,
Description:	147 p.
Notes:	Source: Dissertations Abstracts International, Volume: 80-10, Section: B.
Contained By:	Dissertations Abstracts International80-10B.
Subject:	Computer Engineering. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=13872154
ISBN:	9781392043301

Architectural Techniques for Disturbance Mitigation in Future Memory Systems.
SeyedzadehDelcheh, SeyedMohammad.

Architectural Techniques for Disturbance Mitigation in Future Memory Systems. - Ann Arbor : ProQuest Dissertations & Theses, 2018 - 147 p.

Source: Dissertations Abstracts International, Volume: 80-10, Section: B.

Thesis (Ph.D.)--University of Pittsburgh, 2018.

This item must not be sold to any third party vendors.

With the recent advancements of CMOS technology, scaling down the feature size has improved memory capacity, power, performance and cost. However, such dramatic progress in memory technology has increasingly made the precise control of the manufacturing process below 22nm more difficult. In spite of all these virtues, the technology scaling road map predicts significant process variation from cell-to-cell. It also predicts electromagnetic disturbances among memory cells that easily deviate their circuit characterizations from design goals and pose threats to the reliability, energy efficiency and security. This dissertation proposes simple, energy-efficient and low-overhead techniques that combat the challenges resulting from technology scaling in future memory systems. Specifically, this dissertation investigates solutions tuned to particular types of disturbance challenges, such as inter-cell or intra-cell disturbance, that are energy efficient while guaranteeing memory reliability. The contribution of this dissertation will be threefold. First, it uses a deterministic counter-based approach to target the root of inter-cell disturbances in Dynamic random-access memory (DRAM) and provide further benefits to overall energy consumption while deterministically mitigating inter-cell disturbances. Second, it uses Markov chains to reason about the reliability of Spin-Transfer Torque Magnetic Random-Access Memory (STT-RAM) that suffers from intra-cell disturbances and then investigates on-demand refresh policies to recover from the persistent effect of such disturbances. Third, It leverages an encoding technique integrated with a novel word level compression scheme to reduce the vulnerability of cells to inter-cell write disturbances in Phase Change Memory (PCM). However, mitigating inter-cell write disturbances and also minimizing the write energy may increase the number of updated PCM cells and result in degraded endurance. Hence, It uses multi-objective optimization to balance the write energy and endurance in PCM cells while mitigating inter-cell disturbances. The work in this dissertation provides important insights into how to tackle the critical reliability challenges that high-density memory systems confront in deep scaled technology nodes. It advocates for various memory technologies to guarantee reliability of future memory systems while incurring nominal costs in terms of energy, area and performance.

ISBN: 9781392043301Subjects--Topical Terms:

1567821
Computer Engineering.

Architectural Techniques for Disturbance Mitigation in Future Memory Systems.
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