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Optimized Embedded and Reconfigurabl...

Shahrouzi, Seyed Navid.

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Optimized Embedded and Reconfigurable Hardware Architectures and Techniques for Data Mining Applications on Mobile Devices.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Optimized Embedded and Reconfigurable Hardware Architectures and Techniques for Data Mining Applications on Mobile Devices./
Author:	Shahrouzi, Seyed Navid.
Published:	Ann Arbor : ProQuest Dissertations & Theses, : 2018,
Description:	193 p.
Notes:	Source: Dissertations Abstracts International, Volume: 80-06, Section: B.
Contained By:	Dissertations Abstracts International80-06B.
Subject:	Information Technology. -
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10981514
ISBN:	9780438706071

Optimized Embedded and Reconfigurable Hardware Architectures and Techniques for Data Mining Applications on Mobile Devices.
Shahrouzi, Seyed Navid.

Optimized Embedded and Reconfigurable Hardware Architectures and Techniques for Data Mining Applications on Mobile Devices. - Ann Arbor : ProQuest Dissertations & Theses, 2018 - 193 p.

Source: Dissertations Abstracts International, Volume: 80-06, Section: B.

Thesis (Ph.D.)--University of Colorado Colorado Springs, 2018.

This item must not be sold to any third party vendors.

Increasingly, most of the electronic devices which are surrounding us, are designed in mobile (portable) and embedded systems platforms; therefore, the global market for these devices are growing exponentially. Almost every day, this competitive market offers novel power-efficient and low-cost devices with better features to customers. To reduce the cost and power as well as to increase features of mobile (portable) and embedded devices, many techniques and technologies are being exploited to optimize hardware and overcome stringent constraint such as area, power consumption, memory bandwidths, cost, etc. Nowadays, many applications are running on mobile (portable) and embedded platforms. Most of these applications are dealing with data and data interpretations, and somehow, these applications can be counted as compute and/or data intensive applications such as data-mining applications. Computational complexity of data-mining increases dramatically by increases in amount and size of input data; therefore, optimized and accelerated hardware is needed to overcome this issue. Among embedded platforms of mobile (portable) devices, usage of Field Programmable Gate Arrays (FPGAs) is growing because of many benefits and features of these ICs. These reprogrammable silicon chips provide flexibility to users by having high performance, low time to market, reliability, and long-term maintenance. FPGAs hardware frameworks can be updated with new versions. FPGAs are also provided by many efficient hardware IPs and soft processers, which are essential in embedded systems. These and many other features made FPGAs a good choice for mobile and embedded systems. Our main objective in this research work is to provide optimized and reconfigurable hardware architectures to enhance compute and data intensive applications such as data mining applications running on embedded and mobile devices. We consider and overcome some constraints of embedded and mobile devices such as on-chip occupied area and data access latency from off-chip memories. We create our optimized hardware in embedded systems implemented on FPGAs. We introduce novel optimized embedded hardware architectures for the principal component analysis (PCA) computation which is a common and popular data miming technique to reduce the dimensionality of data by transforming the original data set into new set of variables that represent the key features of the data. PCA is a complex and compute/data intensive data mining technique which is a good choice for our research. We incorporate several hardware optimization techniques to enhance the performance of our designs and to reduce the memory access latency of embedded platforms. Our embedded hardware designs are generic and parameterized; and achieves 78 times speedup compared to its software counterparts. Also, to enhance the area efficiency, we exploit dynamic partial reconfirmation techniques to run the PCA process. Our partial and dynamic reconfigurable hardware achieves 71% space saving compared to its static reconfigurable hardware design. We also come up with multi-ported memory architectures on FPGAs to further enhance hardware acceleration for data and/or compute intensive applications, and to overcome memory bandwidth limitations on FPGAs. We also introduce optimization of hardware description languages (HDLs) codes; this optimization which result in better hardware implementation on FPGAs. Our experiments demonstrate the feasibility and performance improvement in our embedded and reconfigurable architectures as well as our multi-ported memory architectures and HDL optimization.

ISBN: 9780438706071Subjects--Topical Terms:

1030799
Information Technology.

Optimized Embedded and Reconfigurable Hardware Architectures and Techniques for Data Mining Applications on Mobile Devices.
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500 $a Source: Dissertations Abstracts International, Volume: 80-06, Section: B.
500 $a Publisher info.: Dissertation/Thesis.
500 $a Perera, Darshika G.
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506 $a This item must not be sold to any third party vendors.
520 $a Increasingly, most of the electronic devices which are surrounding us, are designed in mobile (portable) and embedded systems platforms; therefore, the global market for these devices are growing exponentially. Almost every day, this competitive market offers novel power-efficient and low-cost devices with better features to customers. To reduce the cost and power as well as to increase features of mobile (portable) and embedded devices, many techniques and technologies are being exploited to optimize hardware and overcome stringent constraint such as area, power consumption, memory bandwidths, cost, etc. Nowadays, many applications are running on mobile (portable) and embedded platforms. Most of these applications are dealing with data and data interpretations, and somehow, these applications can be counted as compute and/or data intensive applications such as data-mining applications. Computational complexity of data-mining increases dramatically by increases in amount and size of input data; therefore, optimized and accelerated hardware is needed to overcome this issue. Among embedded platforms of mobile (portable) devices, usage of Field Programmable Gate Arrays (FPGAs) is growing because of many benefits and features of these ICs. These reprogrammable silicon chips provide flexibility to users by having high performance, low time to market, reliability, and long-term maintenance. FPGAs hardware frameworks can be updated with new versions. FPGAs are also provided by many efficient hardware IPs and soft processers, which are essential in embedded systems. These and many other features made FPGAs a good choice for mobile and embedded systems. Our main objective in this research work is to provide optimized and reconfigurable hardware architectures to enhance compute and data intensive applications such as data mining applications running on embedded and mobile devices. We consider and overcome some constraints of embedded and mobile devices such as on-chip occupied area and data access latency from off-chip memories. We create our optimized hardware in embedded systems implemented on FPGAs. We introduce novel optimized embedded hardware architectures for the principal component analysis (PCA) computation which is a common and popular data miming technique to reduce the dimensionality of data by transforming the original data set into new set of variables that represent the key features of the data. PCA is a complex and compute/data intensive data mining technique which is a good choice for our research. We incorporate several hardware optimization techniques to enhance the performance of our designs and to reduce the memory access latency of embedded platforms. Our embedded hardware designs are generic and parameterized; and achieves 78 times speedup compared to its software counterparts. Also, to enhance the area efficiency, we exploit dynamic partial reconfirmation techniques to run the PCA process. Our partial and dynamic reconfigurable hardware achieves 71% space saving compared to its static reconfigurable hardware design. We also come up with multi-ported memory architectures on FPGAs to further enhance hardware acceleration for data and/or compute intensive applications, and to overcome memory bandwidth limitations on FPGAs. We also introduce optimization of hardware description languages (HDLs) codes; this optimization which result in better hardware implementation on FPGAs. Our experiments demonstrate the feasibility and performance improvement in our embedded and reconfigurable architectures as well as our multi-ported memory architectures and HDL optimization.
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