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Learning from VLSI design experience

Lee, Weng Fook.

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Learning from VLSI design experience

Record Type:	Electronic resources : Monograph/item
Title/Author:	Learning from VLSI design experience/ by Weng Fook Lee.
Author:	Lee, Weng Fook.
Published:	Cham :Springer International Publishing : : 2019.,
Description:	xxix, 214 p. :ill., digital ;24 cm.
[NT 15003449]:	Chapter 1. Introduction -- Chapter 2. Design Methodology and Flow -- Chapter 3. Multiple Clock Design -- Chapter 4. Latch Inference -- Chapter 5. Design for Test -- Chapter 6. Signed Verilog -- Chapter 7. State Machine -- Chapter 8. RTL Coding Guideline -- Chapter 9. Code Coverage.
Contained By:	Springer eBooks
Subject:	Integrated circuits - Very large scale integration -
Online resource:	https://doi.org/10.1007/978-3-030-03238-8
ISBN:	9783030032388

Learning from VLSI design experience
Lee, Weng Fook.

Learning from VLSI design experience[electronic resource] /by Weng Fook Lee. - Cham :Springer International Publishing :2019. - xxix, 214 p. :ill., digital ;24 cm.

Chapter 1. Introduction -- Chapter 2. Design Methodology and Flow -- Chapter 3. Multiple Clock Design -- Chapter 4. Latch Inference -- Chapter 5. Design for Test -- Chapter 6. Signed Verilog -- Chapter 7. State Machine -- Chapter 8. RTL Coding Guideline -- Chapter 9. Code Coverage.

This book shares with readers practical design knowledge gained from the author's 24 years of IC design experience. The author addresses issues and challenges faced commonly by IC designers, along with solutions and workarounds. Guidelines are described for tackling issues such as clock domain crossing, using lockup latch to cross clock domains during scan shift, implementation of scan chains across power domain, optimization methods to improve timing, how standard cell libraries can aid in synthesis optimization, BKM (best known method) for RTL coding, test compression, memory BIST, usage of signed Verilog for design requiring +ve and -ve calculations, state machine, code coverage and much more. Numerous figures and examples are provided to aid the reader in understanding the issues and their workarounds. Addresses practical design issues and their workarounds; Discusses issues such as CDC, crossing clock domain in shift, scan chains across power domain, timing optimization, standard cell library influence on synthesis, DFT, code coverage, state machine; Provides readers with an RTL coding guideline, based on real experience.

ISBN: 9783030032388

Standard No.: 10.1007/978-3-030-03238-8doiSubjects--Topical Terms:

629093
Integrated circuits
--Very large scale integration

LC Class. No.: TK7874.75 / .L449 2019

Dewey Class. No.: 621.395

Learning from VLSI design experience
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245 1 0 $a Learning from VLSI design experience $h [electronic resource] / $c by Weng Fook Lee.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2019.
300 $a xxix, 214 p. : $b ill., digital ; $c 24 cm.
505 0 $a Chapter 1. Introduction -- Chapter 2. Design Methodology and Flow -- Chapter 3. Multiple Clock Design -- Chapter 4. Latch Inference -- Chapter 5. Design for Test -- Chapter 6. Signed Verilog -- Chapter 7. State Machine -- Chapter 8. RTL Coding Guideline -- Chapter 9. Code Coverage.
520 $a This book shares with readers practical design knowledge gained from the author's 24 years of IC design experience. The author addresses issues and challenges faced commonly by IC designers, along with solutions and workarounds. Guidelines are described for tackling issues such as clock domain crossing, using lockup latch to cross clock domains during scan shift, implementation of scan chains across power domain, optimization methods to improve timing, how standard cell libraries can aid in synthesis optimization, BKM (best known method) for RTL coding, test compression, memory BIST, usage of signed Verilog for design requiring +ve and -ve calculations, state machine, code coverage and much more. Numerous figures and examples are provided to aid the reader in understanding the issues and their workarounds. Addresses practical design issues and their workarounds; Discusses issues such as CDC, crossing clock domain in shift, scan chains across power domain, timing optimization, standard cell library influence on synthesis, DFT, code coverage, state machine; Provides readers with an RTL coding guideline, based on real experience.
650 0 $a Integrated circuits $x Very large scale integration $x Design. $3 629093
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856 4 0 $u https://doi.org/10.1007/978-3-030-03238-8
950 $a Engineering (Springer-11647)