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Energy efficient high performance pr...
~
Haj-Yahya, Jawad.
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Energy efficient high performance processors = recent approaches for designing green high performance computing /
Record Type:
Electronic resources : Monograph/item
Title/Author:
Energy efficient high performance processors/ by Jawad Haj-Yahya ... [et al.].
Reminder of title:
recent approaches for designing green high performance computing /
other author:
Haj-Yahya, Jawad.
Published:
Singapore :Springer Singapore : : 2018.,
Description:
xiv, 165 p. :ill. (some col.), digital ;24 cm.
[NT 15003449]:
Introduction -- Background -- DOEE: Dynamic Optimization framework for better Energy Efficiency -- Fine-grain Power Breakdown of Modern Out-Of-Order Cores and its implications on Skylake based systems -- Compiler-Directed Power Management for Superscalars -- SEEM: Symbolic Execution for Energy Modeling -- Related Works -- Conclusions and Future Work.
Contained By:
Springer eBooks
Subject:
High performance computing - Energy consumption. -
Online resource:
http://dx.doi.org/10.1007/978-981-10-8554-3
ISBN:
9789811085543
Energy efficient high performance processors = recent approaches for designing green high performance computing /
Energy efficient high performance processors
recent approaches for designing green high performance computing /[electronic resource] :by Jawad Haj-Yahya ... [et al.]. - Singapore :Springer Singapore :2018. - xiv, 165 p. :ill. (some col.), digital ;24 cm. - Computer architecture and design methodologies,2367-3478. - Computer architecture and design methodologies..
Introduction -- Background -- DOEE: Dynamic Optimization framework for better Energy Efficiency -- Fine-grain Power Breakdown of Modern Out-Of-Order Cores and its implications on Skylake based systems -- Compiler-Directed Power Management for Superscalars -- SEEM: Symbolic Execution for Energy Modeling -- Related Works -- Conclusions and Future Work.
This book explores energy efficiency techniques for high-performance computing (HPC) systems using power-management methods. Adopting a step-by-step approach, it describes power-management flows, algorithms and mechanism that are employed in modern processors such as Intel Sandy Bridge, Haswell, Skylake and other architectures (e.g. ARM) Further, it includes practical examples and recent studies demonstrating how modem processors dynamically manage wide power ranges, from a few milliwatts in the lowest idle power state, to tens of watts in turbo state. Moreover, the book explains how thermal and power deliveries are managed in the context this huge power range. The book also discusses the different metrics for energy efficiency, presents several methods and applications of the power and energy estimation, and shows how by using innovative power estimation methods and new algorithms modern processors are able to optimize metrics such as power, energy, and performance. Different power estimation tools are presented, including tools that break down the power consumption of modern processors at sub-processor core/thread granularity. The book also investigates software, firmware and hardware coordination methods of reducing power consumption, for example a compiler-assisted power management method to overcome power excursions. Lastly, it examines firmware algorithms for dynamic cache resizing and dynamic voltage and frequency scaling (DVFS) for memory sub-systems.
ISBN: 9789811085543
Standard No.: 10.1007/978-981-10-8554-3doiSubjects--Topical Terms:
3308753
High performance computing
--Energy consumption.
LC Class. No.: QA76.88
Dewey Class. No.: 004.3
Energy efficient high performance processors = recent approaches for designing green high performance computing /
LDR
:02918nmm a2200325 a 4500
001
2136911
003
DE-He213
005
20180927100203.0
006
m d
007
cr nn 008maaau
008
181117s2018 si s 0 eng d
020
$a
9789811085543
$q
(electronic bk.)
020
$a
9789811085536
$q
(paper)
024
7
$a
10.1007/978-981-10-8554-3
$2
doi
035
$a
978-981-10-8554-3
040
$a
GP
$c
GP
041
0
$a
eng
050
4
$a
QA76.88
072
7
$a
TJFC
$2
bicssc
072
7
$a
TEC008010
$2
bisacsh
082
0 4
$a
004.3
$2
23
090
$a
QA76.88
$b
.E56 2018
245
0 0
$a
Energy efficient high performance processors
$h
[electronic resource] :
$b
recent approaches for designing green high performance computing /
$c
by Jawad Haj-Yahya ... [et al.].
260
$a
Singapore :
$b
Springer Singapore :
$b
Imprint: Springer,
$c
2018.
300
$a
xiv, 165 p. :
$b
ill. (some col.), digital ;
$c
24 cm.
490
1
$a
Computer architecture and design methodologies,
$x
2367-3478
505
0
$a
Introduction -- Background -- DOEE: Dynamic Optimization framework for better Energy Efficiency -- Fine-grain Power Breakdown of Modern Out-Of-Order Cores and its implications on Skylake based systems -- Compiler-Directed Power Management for Superscalars -- SEEM: Symbolic Execution for Energy Modeling -- Related Works -- Conclusions and Future Work.
520
$a
This book explores energy efficiency techniques for high-performance computing (HPC) systems using power-management methods. Adopting a step-by-step approach, it describes power-management flows, algorithms and mechanism that are employed in modern processors such as Intel Sandy Bridge, Haswell, Skylake and other architectures (e.g. ARM) Further, it includes practical examples and recent studies demonstrating how modem processors dynamically manage wide power ranges, from a few milliwatts in the lowest idle power state, to tens of watts in turbo state. Moreover, the book explains how thermal and power deliveries are managed in the context this huge power range. The book also discusses the different metrics for energy efficiency, presents several methods and applications of the power and energy estimation, and shows how by using innovative power estimation methods and new algorithms modern processors are able to optimize metrics such as power, energy, and performance. Different power estimation tools are presented, including tools that break down the power consumption of modern processors at sub-processor core/thread granularity. The book also investigates software, firmware and hardware coordination methods of reducing power consumption, for example a compiler-assisted power management method to overcome power excursions. Lastly, it examines firmware algorithms for dynamic cache resizing and dynamic voltage and frequency scaling (DVFS) for memory sub-systems.
650
0
$a
High performance computing
$x
Energy consumption.
$3
3308753
650
0
$a
High performance processors.
$3
1569786
650
1 4
$a
Engineering.
$3
586835
650
2 4
$a
Circuits and Systems.
$3
896527
650
2 4
$a
Processor Architectures.
$3
892680
650
2 4
$a
Electronic Circuits and Devices.
$3
1245773
700
1
$a
Haj-Yahya, Jawad.
$3
3308752
710
2
$a
SpringerLink (Online service)
$3
836513
773
0
$t
Springer eBooks
830
0
$a
Computer architecture and design methodologies.
$3
2203505
856
4 0
$u
http://dx.doi.org/10.1007/978-981-10-8554-3
950
$a
Engineering (Springer-11647)
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