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Fault tolerant architectures for cry...

Patranabis, Sikhar.

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Fault tolerant architectures for cryptography and hardware security

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Fault tolerant architectures for cryptography and hardware security/ edited by Sikhar Patranabis, Debdeep Mukhopadhyay.
其他作者:	Patranabis, Sikhar.
出版者:	Singapore :Springer Singapore : : 2018.,
面頁冊數:	xii, 240 p. :ill., digital ;24 cm.
內容註:	Introduction to Fault Analysis -- Classical Fault Analysis -- Recent Trends and Advances in Fault Analysis -- Automation of Fault Analysis -- Countermeasures and Fault Tolerant Architectures -- Practical Perspectives of Fault Tolerant Design.
Contained By:	Springer eBooks
標題:	Fault-tolerant computing. -
電子資源:	http://dx.doi.org/10.1007/978-981-10-1387-4
ISBN:	9789811013874

Fault tolerant architectures for cryptography and hardware security
Fault tolerant architectures for cryptography and hardware security[electronic resource] /edited by Sikhar Patranabis, Debdeep Mukhopadhyay. - Singapore :Springer Singapore :2018. - xii, 240 p. :ill., digital ;24 cm. - Computer architecture and design methodologies,2367-3478. - Computer architecture and design methodologies..

Introduction to Fault Analysis -- Classical Fault Analysis -- Recent Trends and Advances in Fault Analysis -- Automation of Fault Analysis -- Countermeasures and Fault Tolerant Architectures -- Practical Perspectives of Fault Tolerant Design.

This book uses motivating examples and real-life attack scenarios to introduce readers to the general concept of fault attacks in cryptography. It offers insights into how the fault tolerance theories developed in the book can actually be implemented, with a particular focus on a wide spectrum of fault models and practical fault injection techniques, ranging from simple, low-cost techniques to high-end equipment-based methods. It then individually examines fault attack vulnerabilities in symmetric, asymmetric and authenticated encryption systems. This is followed by extensive coverage of countermeasure techniques and fault tolerant architectures that attempt to thwart such vulnerabilities. Lastly, it presents a case study of a comprehensive FPGA-based fault tolerant architecture for AES-128, which brings together of a number of the fault tolerance techniques presented. It concludes with a discussion on how fault tolerance can be combined with side channel security to achieve protection against implementation-based attacks. The text is supported by illustrative diagrams, algorithms, tables and diagrams presenting real-world experimental results.

ISBN: 9789811013874

Standard No.: 10.1007/978-981-10-1387-4doiSubjects--Topical Terms:

649213
Fault-tolerant computing.

LC Class. No.: QA76.9.F38 / F385 2018

Dewey Class. No.: 005.1

Fault tolerant architectures for cryptography and hardware security
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490 1 $a Computer architecture and design methodologies, $x 2367-3478
505 0 $a Introduction to Fault Analysis -- Classical Fault Analysis -- Recent Trends and Advances in Fault Analysis -- Automation of Fault Analysis -- Countermeasures and Fault Tolerant Architectures -- Practical Perspectives of Fault Tolerant Design.
520 $a This book uses motivating examples and real-life attack scenarios to introduce readers to the general concept of fault attacks in cryptography. It offers insights into how the fault tolerance theories developed in the book can actually be implemented, with a particular focus on a wide spectrum of fault models and practical fault injection techniques, ranging from simple, low-cost techniques to high-end equipment-based methods. It then individually examines fault attack vulnerabilities in symmetric, asymmetric and authenticated encryption systems. This is followed by extensive coverage of countermeasure techniques and fault tolerant architectures that attempt to thwart such vulnerabilities. Lastly, it presents a case study of a comprehensive FPGA-based fault tolerant architecture for AES-128, which brings together of a number of the fault tolerance techniques presented. It concludes with a discussion on how fault tolerance can be combined with side channel security to achieve protection against implementation-based attacks. The text is supported by illustrative diagrams, algorithms, tables and diagrams presenting real-world experimental results.
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